公开(公告)号：US20150123171A1

公开(公告)日：2015-05-07

申请号：US14597128

申请日：2015-01-14

Applicant: MARKO RADOSAVLJEVIC ,  PRASHANT MAJHI ,  JACK T. KAVALIEROS ,  NITI GOEL ,  WILMAN TSAI ,  NILOY MUKHERJEE ,  YONG JU LEE ,  GILBERT DEWEY ,  WILLY RACHMADY

Inventor： MARKO RADOSAVLJEVIC ,  PRASHANT MAJHI ,  JACK T. KAVALIEROS ,  NITI GOEL ,  WILMAN TSAI ,  NILOY MUKHERJEE ,  YONG JU LEE ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L29/778 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L21/2256 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/47 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.

Abstract translation: 描述了III-V半导体器件的电导率改进。 第一改进包括与通道层不共同平面的阻挡层。 第二个改进包括金属/ Si，Ge或硅锗/ III-V堆叠的退火，以在Si和/或锗掺杂的III-V层上形成金属硅，金属锗或金属硅锗层。 然后，去除金属层并在金属硅，金属锗或金属硅锗层上形成源/漏电极。 第三个改进包括在III-V沟道层上形成IV族和/或VI族元素的层，以及退火以使IV族和/或VI族物质掺杂III-V通道层。 第四个改进包括在III-V器件的接近区域上形成的钝化层和/或偶极层。

公开(公告)号：US09006707B2

公开(公告)日：2015-04-14

申请号：US11712191

申请日：2007-02-28

Applicant: Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

Inventor： Mantu K. Hudait ,  Jack T. Kavalieros ,  Suman Datta ,  Marko Radosavljevic

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/8252 ,  B82Y10/00 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/04

CPC classification number: H01L21/823807 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/0605 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/151 ,  H01L29/201 ,  H01L29/207 ,  H01L29/365

Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于形成逻辑器件的方法，包括在硅（Si）衬底上形成n型半导体器件，该衬底包括基于砷化铟镓（InGaAs）的堆叠，其包括第一缓冲层， 形成在第一缓冲层上的第二缓冲层，形成在第二缓冲层上的第一器件层。 此外，该方法可以包括从基于InGaAs的叠层在Si衬底上形成p型半导体器件，并且在n型半导体器件和p型半导体器件之间形成隔离。 描述和要求保护其他实施例。

公开(公告)号：US08921830B2

公开(公告)日：2014-12-30

申请号：US13461962

申请日：2012-05-02

Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66977 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7842 ,  H01L29/785

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种具有衬底，形成在衬底上的掩埋氧化物层，形成在掩埋氧化物层上的绝缘体上硅（SOI）芯体，围绕着该衬底的压应变量子阱（QW）层） SOI芯，以及围绕QW层缠绕的拉伸应变硅层。 描述和要求保护其他实施例。

公开(公告)号：US08878363B2

公开(公告)日：2014-11-04

申请号：US12459254

申请日：2009-06-26

Applicant: Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/47 ,  H01L23/485 ,  H01L29/78 ,  H01L21/285 ,  H01L23/532 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/517 ,  H01B1/122 ,  H01L21/048 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/7853 ,  H01L31/022466 ,  H01L31/022475 ,  H01L33/0041 ,  H01L33/40 ,  H01L45/08 ,  H01L45/1206 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/145 ,  H01L51/102 ,  H01L51/105 ,  H01L51/441 ,  H01L51/442 ,  H01L51/5203 ,  H01L51/5234 ,  H01L2251/301 ,  H01L2251/303 ,  H01L2251/306 ,  H01L2251/308 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

Abstract translation: 使用中间层来减少具有半导体衬底的半导体器件中的费米能级钉扎现象。 中间层可以是稀土氧化物。 中间层可以是离子半导体。 金属阻挡膜可以设置在中间层和金属耦合器之间。 中间层可以是金属阻挡膜和半导体基板的热处理组合。 形成中间层的方法可以包括对中间层进行分级。 计算系统包括中间层。

公开(公告)号：US08847281B2

公开(公告)日：2014-09-30

申请号：US13560474

申请日：2012-07-27

Applicant: Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

Inventor： Stephen M. Cea ,  Anand S. Murthy ,  Glenn A. Glass ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Roza Kotlyar

IPC: H01L29/165

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.

Abstract translation: 公开了用于将高迁移率应变通道结合到鳍状晶体管（例如，诸如双栅极，三相等等的FinFET）中的技术，其中应力材料被包覆到鳍的沟道区域上。 在一个示例性实施例中，硅锗（SiGe）被包覆到硅散热片上以提供期望的应力，尽管可以使用其它鳍和包层材料。 这些技术与典型的工艺流程兼容，并且包层沉积可以发生在工艺流程内的多个位置处。 在一些情况下，来自包覆层的内置应力可以通过压缩通道中的鳍和覆层的源极/漏极应力来增强。 在一些情况下，可以提供可选的封盖层以改善栅极电介质/半导体界面。 在一个这样的实施例中，硅被提供在SiGe包覆层上以改善栅极电介质/半导体界面。

公开(公告)号：US20140091361A1

公开(公告)日：2014-04-03

申请号：US13631417

申请日：2012-09-28

Applicant: Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

公开(公告)号：US20140070273A1

公开(公告)日：2014-03-13

申请号：US14018867

申请日：2013-09-05

Applicant: Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

Inventor： Stephen M. Cea ,  Roza Kotlyar ,  Jack T. Kavalieros ,  Martin D. Giles ,  Tahir Ghani ,  Kelin J. Kuhn ,  Markus Kuhn ,  Nancy M. Zelick

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom.

Abstract translation: 根据该方法制造的方法和装置。 该方法包括提供包括第一材料的基底，并且提供包括第二材料的翅片，所述翅片设置在所述基底上并且具有器件活性部分，所述第一材料和所述第二材料在其各自的结晶结构之间呈现晶格失配 。 提供散热片包括在基板上提供包括第二材料的双轴应变膜; 并除去双轴应变膜的部分以形成基本上单轴应变的翅片。

公开(公告)号：US20130292698A1

公开(公告)日：2013-11-07

申请号：US13976840

申请日：2011-12-23

Applicant: Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Uday Shah ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7787 ,  H01L21/02241 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/31111 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/365 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66462

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

公开(公告)号：US20130146845A1

公开(公告)日：2013-06-13

申请号：US13758974

申请日：2013-02-04

Applicant: Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radiosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Benjamin Chu-Kung ,  Mantu K. Hudait ,  Marko Radiosavljevic ,  Jack T. Kavalieros ,  Willy Rachmady ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/775

CPC classification number: H01L29/7784 ,  H01L29/151 ,  H01L29/155 ,  H01L29/201 ,  H01L29/205 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/775 ,  H01L29/7783 ,  H01L29/78

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract translation: 公开了用于向半导体异质结构中形成的器件提供低电阻自对准触点的技术。 这些技术可以用于例如形成与在III-V和SiGe / Ge材料系统中制造的量子阱晶体管的栅极，源极和漏极区的接触。 不同于在源极/漏极接触到栅极之间的相对大的空间的常规接触工艺流程，由本文所描述的技术提供的所得到的源极和漏极触点是自对准的，因为每个触点与栅电极对准并且被隔离 通过间隔材料。

公开(公告)号：US08384128B2

公开(公告)日：2013-02-26

申请号：US12454354

申请日：2009-05-15

Applicant: Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

Inventor： Ravi Pillarisetty ,  Mantu Uudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/66

CPC classification number: H01L29/66522 ,  H01L29/1054 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66477

Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

Abstract translation: 表面沟道晶体管设置在半导体器件中。 表面沟道晶体管是PMOS或NMOS器件。 外延层设置在表面沟道晶体管的上方，导致更接近器件表面的带隙现象增加。 形成表面沟道晶体管的工艺包括对外延层进行分级。