公开(公告)号：US5427967A

公开(公告)日：1995-06-27

申请号：US31373

申请日：1993-03-11

申请人： S. M. Reza Sadjadi ,  Jeffrey R. Perry

发明人： S. M. Reza Sadjadi ,  Jeffrey R. Perry

IPC分类号： G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

CPC分类号： H01L27/11517 ,  H01L27/115 ,  H01L29/511

摘要： There is disclosed herein a technique for manufacturing a group of memory cells or devices on a common oxide coated silicon substrate such that the cells are arranged in rows and columns with row and column spaces separating the individual cells from one another. Each of the cells includes an array of different layers on the oxide coated top surface of the substrate including, in particular, the polysilicon layer. As disclosed, a method is provided for preventing the formation of polysilicon stringers between individual cells during their manufacture. This method is carried out by first forming the columns before the rows are formed such that continuous sidewalls of the columns are exposed to the ambient surroundings. Thereafter, these sidewalls are coated with protective layers, specifically layers of nitride.

摘要翻译： 这里公开了一种用于在共同的氧化物涂覆的硅衬底上制造一组存储器单元或器件的技术，使得电池以行和列排列成行和列间隔，以将各个电池彼此分开。 每个电池包括在衬底的氧化物涂覆的顶表面上的不同层的阵列，特别是包括多晶硅层。 如所公开的，提供了一种用于在其制造期间防止在单个电池之间形成多晶硅桁条的方法。 该方法是通过在形成行之前首先形成柱，以使柱的连续侧壁暴露于周围环境来进行的。 此后，这些侧壁涂有保护层，特别是氮化层。

公开(公告)号：US5383018A

公开(公告)日：1995-01-17

申请号：US997226

申请日：1992-12-28

申请人： S. M. Reza Sadjadi

发明人： S. M. Reza Sadjadi

IPC分类号： G01N21/93 ,  H01L23/544 ,  G01J1/02 ,  G01N21/88

CPC分类号： H01L22/34 ,  G01N21/93

摘要： A calibration wafer for a patterned wafer scanner is constructed from a substrate of semiconductor material, typically silicon, in which a pattern of features has been etched into the periphery of each die by means of photolithographic techniques. Next, a layer or layers of films composed of materials which are typically used during the fabrication of integrated circuits are deposited. Then a substantially uniform distribution of particles of a known material and size distribution is deposited onto the wafer. A second embodiment of the calibration wafer is one in which a layer or layers of film are first deposited onto a substrate. Then a pattern of features is etched into the periphery of the film covering each die by means of photolithographic techniques. After this step, a substantially uniform distribution of particles is deposited. A method of using such a calibration wafer to calibrate a patterned wafer scanner is also disclosed.

摘要翻译： 用于图案化晶片扫描仪的校准晶片由半导体材料的衬底（通常为硅）构成，其中特征图案已经通过光刻技术蚀刻到每个管芯的外围。 接下来，沉积由在集成电路的制造期间通常使用的材料构成的一层或多层膜。 然后将已知材料和尺寸分布的颗粒的基本上均匀的分布沉积到晶片上。 校准晶片的第二实施例是其中首先将膜层沉积到衬底上的膜。 然后通过光刻技术将特征图案蚀刻到覆盖每个管芯的膜的周边。 在该步骤之后，沉积基本均匀的颗粒分布。 还公开了使用这种校准晶片校准图案化晶片扫描器的方法。

公开(公告)号：US08986492B2

公开(公告)日：2015-03-24

申请号：US13369651

申请日：2012-02-09

申请人： S. M. Reza Sadjadi ,  Amit Jain

发明人： S. M. Reza Sadjadi ,  Amit Jain

IPC分类号： C23F1/00 ,  H01L21/306 ,  H01L21/033

CPC分类号： H01L21/0337

摘要： A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area.

摘要翻译： 一种用于形成具有周围周边区域的阵列区域的方法，其中衬底设置在蚀刻层下方，其设置在限定阵列区域并覆盖整个周边区域的图案化有机掩模下方。 图案化的有机面罩被修剪。 在图案化的有机掩模上沉积无机层，其中在有机掩模的被覆盖的周边区域上的无机层的厚度大于无机层在有机掩模的阵列区域上的厚度。 将无机层回蚀刻以露出有机掩模并在阵列区域中形成无机间隔物，同时将外围区域中的有机掩模留置不暴露。 剥离在阵列区域中暴露的有机掩模，同时将无机间隔物留在适当位置并保护外围区域中的有机掩模。

公开(公告)号：US08864931B2

公开(公告)日：2014-10-21

申请号：US12907899

申请日：2010-10-19

申请人： Supriya Goyal ,  Dongho Heo ,  Jisoo Kim ,  S. M. Reza Sadjadi

发明人： Supriya Goyal ,  Dongho Heo ,  Jisoo Kim ,  S. M. Reza Sadjadi

IPC分类号： H01L21/306 ,  C23F1/00 ,  H01L21/033

CPC分类号： H01L21/0338

摘要： A method for etching a dielectric layer is provided. A patterned mask with mask features is formed over a dielectric layer. The mask has isolated areas and dense areas of the mask features. The mask is trimmed by a plurality of cycles, where each cycle includes depositing a deposition layer, and selectively etching the deposition layer and the patterned mask. The selective etching selectively trims the isolated areas of the mask with respect to the dense areas of the mask. The dielectric layer is etched using the thus trimmed mask. The mask is removed.

摘要翻译： 提供了蚀刻介电层的方法。 在介电层上形成具有掩模特征的图案化掩模。 面具具有隔离区域和密集区域的面具功能。 掩模被多个周期修剪，其中每个周期包括沉积沉积层，以及选择性地蚀刻沉积层和图案化掩模。 选择性蚀刻相对于掩模的密集区域选择性地修剪掩模的隔离区域。 使用如此修整的掩模蚀刻电介质层。 去除面具。

公开(公告)号：US08592318B2

公开(公告)日：2013-11-26

申请号：US12742073

申请日：2008-11-07

申请人： Jisoo Kim ,  Conan Chiang ,  Jun Shinagawa ,  S. M. Reza Sadjadi

发明人： Jisoo Kim ,  Conan Chiang ,  Jun Shinagawa ,  S. M. Reza Sadjadi

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： H01L21/31144 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31612 ,  H01L21/31654 ,  H01L21/32139

摘要： A method for etching an etch layer disposed over a substrate and below an antireflective coating (ARC) layer and a patterned organic mask with mask features is provided. The substrate is placed in a process chamber. The ARC layer is opened. An oxide spacer deposition layer is formed. The oxide spacer deposition layer on the organic mask is partially removed, where at least the top portion of the oxide spacer deposition layer is removed. The organic mask and the ARC layer are removed by etching. The etch layer is etched through the sidewalls of the oxide spacer deposition layer. The substrate is removed from the process chamber.

摘要翻译： 提供了一种用于蚀刻设置在基板上方并且在抗反射涂层（ARC）层下方的蚀刻层和具有掩模特征的图案化有机掩模的方法。 将基板放置在处理室中。 ARC层打开。 形成氧化物间隔物沉积层。 部分去除有机掩模上的氧化物间隔物沉积层，其中氧化物间隔物沉积层的至少顶部被去除。 通过蚀刻除去有机掩模和ARC层。 通过氧化物隔离层沉积层的侧壁蚀刻蚀刻层。 将衬底从处理室中取出。

公开(公告)号：US08357434B1

公开(公告)日：2013-01-22

申请号：US11304223

申请日：2005-12-13

申请人： Dae-han Choi ,  Jisoo Kim ,  Eric Hudson ,  Sangheon Lee ,  Conan Chiang ,  S. M. Reza Sadjadi

发明人： Dae-han Choi ,  Jisoo Kim ,  Eric Hudson ,  Sangheon Lee ,  Conan Chiang ,  S. M. Reza Sadjadi

IPC分类号： H05H1/24

CPC分类号： H01L21/0338 ,  H01J37/32082 ,  H01J37/32449 ,  H01J37/32724 ,  H01J37/32834

摘要： A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film.

摘要翻译： 公开了一种在等离子体处理系统的等离子体处理室中的基板上沉积保形膜的方法，该基板设置在卡盘上，该卡盘与冷却装置连接。 该方法包括在第一压力下将第一气体混合物流入等离子体处理室，其中第一气体混合物至少包括碳，并且其中第一气体混合物具有冷凝温度。 该方法还包括使用冷却装置将夹盘冷却至冷凝温度以下，从而允许至少一些第一气体混合物在基板的表面上冷凝。 该方法还包括从处理室排出第一气体混合物; 将第二气体混合物流入等离子体处理室，第二气体混合物的组成与第一气体混合物不同; 并冲击等离子体以形成保形膜。

公开(公告)号：US08282847B2

公开(公告)日：2012-10-09

申请号：US12338947

申请日：2008-12-18

申请人： Andrew R. Romano ,  S. M. Reza Sadjadi

发明人： Andrew R. Romano ,  S. M. Reza Sadjadi

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/311

CPC分类号： G03F7/40 ,  G03F7/0035 ,  G03F7/405 ,  H01L21/76816

摘要： A method for etching an etch layer formed on a substrate is provided. A first photoresist (PR) mask with first mask features is provided on the etch layer. A protective coating is provided on the first PR mask by a process including at least one cycle. Each cycle includes (a) a deposition phase for depositing a deposition layer over the surface of the first mask features using a deposition gas, and (b) a profile shaping phase for shaping the profile of the deposition layer using a profile shaping gas. A liquid PR material is applied over the first PR mask having the protective coating. The PR material is patterned into a second mask features, where the first and second mask features form a second PR mask. The etch layer is etched though the second PR mask.

摘要翻译： 提供蚀刻形成在基板上的蚀刻层的方法。 在蚀刻层上提供具有第一掩模特征的第一光致抗蚀剂（PR）掩模。 通过包括至少一个循环的工艺在第一PR掩模上提供保护涂层。 每个循环包括（a）用于使用沉积气体在第一掩模特征的表面上沉积沉积层的沉积阶段，以及（b）用于使用轮廓成形气体成形沉积层的轮廓的轮廓成形相。 在具有保护涂层的第一PR掩模上施加液体PR材料。 PR材料被图案化成第二掩模特征，其中第一和第二掩模特征形成第二PR掩模。 通过第二PR掩模蚀刻蚀刻层。

公开(公告)号：US20120205819A1

公开(公告)日：2012-08-16

申请号：US13457147

申请日：2012-04-26

申请人： S. M. Reza Sadjadi ,  Zhi-Song Huang

发明人： S. M. Reza Sadjadi ,  Zhi-Song Huang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76843 ,  H01L23/4821 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

摘要翻译： 提供一种降低半导体器件之间的电容的方法。 在电介质层中形成多个接触结构。 形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。 掩模特征的宽度随着侧壁沉积而收缩。 间隙通过侧壁沉积蚀刻到介电层中。 间隙封闭以形成间隙中的凹坑。

公开(公告)号：US08138092B2

公开(公告)日：2012-03-20

申请号：US12351640

申请日：2009-01-09

申请人： S. M. Reza Sadjadi ,  Amit Jain

发明人： S. M. Reza Sadjadi ,  Amit Jain

IPC分类号： H01L21/311

CPC分类号： H01L21/0337

摘要： A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area.

摘要翻译： 一种用于形成具有周围周边区域的阵列区域的方法，其中衬底设置在蚀刻层下方，其设置在限定阵列区域并覆盖整个周边区域的图案化有机掩模下方。 图案化的有机面罩被修剪。 在图案化的有机掩模上沉积无机层，其中在有机掩模的被覆盖的周边区域上的无机层的厚度大于无机层在有机掩模的阵列区域上的厚度。 将无机层回蚀刻以露出有机掩模并在阵列区域中形成无机间隔物，同时将外围区域中的有机掩模留置不暴露。 剥离在阵列区域中暴露的有机掩模，同时将无机间隔物留在适当位置并保护外围区域中的有机掩模。

公开(公告)号：US20110281435A1

公开(公告)日：2011-11-17

申请号：US13189416

申请日：2011-07-22

申请人： S. M. Reza Sadjadi ,  Zhisong Huang ,  Jose Tong Sam ,  Eric H. Lenz ,  Rajinder Dhindsa

发明人： S. M. Reza Sadjadi ,  Zhisong Huang ,  Jose Tong Sam ,  Eric H. Lenz ,  Rajinder Dhindsa

IPC分类号： H01L21/311

CPC分类号： H01J37/32091 ,  H01J37/32155 ,  H01J37/3244 ,  H01J37/32449

摘要： A plasma chamber with a plasma confinement zone with an electrode is provided. A gas distribution system for providing a first gas and a second gas is connected to the plasma chamber, wherein the gas distribution system can substantially replace one gas in the plasma zone with the other gas within a period of less than 1 s. A first frequency tuned RF power source for providing power to the electrode in a first frequency range is electrically connected to the at least one electrode wherein the first frequency tuned RF power source is able to minimize a reflected RF power. A second frequency tuned RF power source for providing power to the plasma chamber in a second frequency range outside of the first frequency range wherein the second frequency tuned RF power source is able to minimize a reflected RF power.

摘要翻译： 提供具有电极等离子体限制区的等离子体室。 用于提供第一气体和第二气体的气体分配系统连接到等离子体室，其中气体分配系统可以在小于1秒的时间内基本上替换等离子体区域中的一种气体与另一种气体。 用于在第一频率范围内向电极提供功率的第一频率调谐RF电源电连接到至少一个电极，其中第一频率调谐的RF功率源能够最小化反射的RF功率。 用于在第一频率范围之外的第二频率范围内为等离子体室提供功率的第二频率调谐RF电源，其中第二频率调谐的RF功率源能够使反射的RF功率最小化。