公开(公告)号：US20190288157A1

公开(公告)日：2019-09-19

申请号：US16352029

申请日：2019-03-13

Applicant: Soitec

Inventor： Jean-Marc Bethoux ,  Morgane Logiou ,  Raphaél Caulmilone

IPC: H01L33/00 ,  H01L33/06 ,  H01L33/32 ,  H01L27/15 ,  H01L31/18

Abstract: A method for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters includes the following steps: providing a relaxation substrate that comprises a medium, a flow layer disposed on the medium and, a plurality of strained crystalline semiconductor islands having an initial lattice parameter located on the flow layer, a first group of islands having a first lattice parameter and a second group of islands having a second lattice parameter that is different from the first; and heat treating the relaxation substrate at a relaxation temperature greater than or equal to the glass transition temperature of the flow layer to cause differentiated lateral expansion of the islands of the first and second group. The lattice parameter of the relaxed islands of the first group and the relaxed islands of the second group then have different values.

公开(公告)号：US20190267425A1

公开(公告)日：2019-08-29

申请号：US16340879

申请日：2017-10-10

Applicant: Soitec

Inventor： Walter Schwarzenbach

IPC: H01L27/146 ,  H01L21/762

Abstract: A front-side type image sensor, includes a substrate successively comprising a P− type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate, wherein the substrate comprises, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer A method of forming such a structure includes epitaxially growing a P+ type doped semiconducting layer on a P− type doped semiconducting support substrate, providing an electrically insulating layer and an active layer over the P+ type doped semiconducting layer, and forming photodiodes in the active layer.

公开(公告)号：US20190259617A1

公开(公告)日：2019-08-22

申请号：US16342133

申请日：2017-09-29

Applicant: Soitec

Inventor： Frederic Allibert

IPC: H01L21/225 ,  H01L21/762

Abstract: A method for dissolving a buried oxide in a silicon-on-insulator wafer comprises providing a silicon-on-insulator wafer having a silicon layer attached to a carrier substrate via a buried oxide layer, and annealing the silicon-on-insulator wafer to at least partially dissolve the buried oxide layer. The method further comprises a step of providing an oxygen scavenging layer on or over the silicon layer before the annealing step.

公开(公告)号：US10250282B2

公开(公告)日：2019-04-02

申请号：US15531976

申请日：2015-09-17

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Didier Landru ,  Christophe Figuet

IPC: H04B1/38 ,  H04B1/03 ,  H01L21/02 ,  H01L21/762 ,  H01M4/66 ,  H01L21/28 ,  H01L41/047

Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower than 10,000 ohm·cm over a temperature range extending from −20° C. to 120° C.

公开(公告)号：US20180316329A1

公开(公告)日：2018-11-01

申请号：US15769698

申请日：2016-10-17

Applicant: Soitec

Inventor： Pascal Guenard ,  Ionut Radu ,  Didier Landru ,  Eric Desbonnets

IPC: H03H3/04 ,  H01L41/053 ,  H01L41/312 ,  H03H9/02 ,  H03H9/05

CPC classification number: H01L41/312 ,  H01L41/0805 ,  H03H9/02102 ,  H03H9/02574

Abstract: A composite structure for an acoustic wave device comprising a heterostructure includes: a useful layer of piezoelectric material, having a first face and a second face, the first face being arranged at a first bonding interface on a support substrate having a coefficient of thermal expansion less than that of the useful layer, wherein the composite structure further comprises a functional layer, an entire surface of which is arranged at a second bonding interface on the second face of the useful layer and having a coefficient of thermal expansion less than that of the useful layer. Methods are used for producing such a composite structure.

公开(公告)号：US10014429B2

公开(公告)日：2018-07-03

申请号：US14749334

申请日：2015-06-24

Applicant: Soitec

Inventor： Fred Newman ,  Frank Reinhardt ,  Chantal Arena

IPC: H01L31/06 ,  H01L31/04 ,  H01L31/18 ,  H01L31/0687 ,  H01L31/0693 ,  H01L31/0304 ,  H01L31/043

CPC classification number: H01L31/0687 ,  H01L31/03042 ,  H01L31/03046 ,  H01L31/03048 ,  H01L31/043 ,  H01L31/0693 ,  H01L31/184 ,  H01L31/1844 ,  H01L31/1852 ,  H01L31/1892 ,  Y02E10/544

Abstract: A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on a major surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.

公开(公告)号：US09978905B2

公开(公告)日：2018-05-22

申请号：US15141472

申请日：2016-04-28

Applicant: Soitec

Inventor： Jean-Philippe Debray ,  Chantal Arena ,  Heather McFavilen

IPC: H01L33/06 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/14 ,  H01L21/02

CPC classification number: H01L33/06 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L33/007 ,  H01L33/12 ,  H01L33/145 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1−wN, and at least one barrier layer comprising InbGa1−bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1−wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1−bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.

公开(公告)号：US20180102264A1

公开(公告)日：2018-04-12

申请号：US15728953

申请日：2017-10-10

Applicant: Soitec

Inventor： Didier Landru ,  Oleg Kononchuk ,  Sébastien Simon

IPC: H01L21/67 ,  H01L21/677 ,  F27D7/06 ,  F27D5/00

Abstract: A thermal treatment system includes a chamber capable of receiving a plurality of substrates, a gas intake path in a distal portion of the chamber located opposite an area for entry of substrates into the chamber, and an outlet path for the gas and/or volatile species generated during the thermal treatment. The outlet path is located in a proximal portion of the chamber located near the area for entry of the substrates into the chamber. The system further includes a collector device in the proximal portion of the chamber. The collector device has a confinement opening oriented toward the distal portion of the chamber, and the collector device defines a compartment communicating with the outlet path, the compartment being configured so that the gas and the volatile species enter into the compartment via the confinement opening and pass through the compartment to reach the outlet path.

公开(公告)号：US09905531B2

公开(公告)日：2018-02-27

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/306 ,  H01L21/66

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

公开(公告)号：US09887124B2

公开(公告)日：2018-02-06

申请号：US14900257

申请日：2014-06-17

Applicant: Soitec

Inventor： Nadia Ben Mohamed ,  Eric Maze

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/42 ,  H01L21/00 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/76254 ,  H01L21/02236 ,  H01L21/30604

Abstract: A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support substrate; b) forming a zone of weakening in the donor substrate, the zone of weakening delimiting, with the first surface of the donor substrate, a working layer; c) assembling the support substrate and the donor substrate; d) fracturing the donor substrate along the zone of weakening; and e) thinning the working layer so as to form a thinned working layer. Stage b) is carried out so that the working layer exhibits a thickness profile appropriate for compensating for the nonuniformity in consumption of the working layer during stage e).