Localized stress modulation for overlay and EPE

    公开(公告)号:US09748148B2

    公开(公告)日:2017-08-29

    申请号:US14736020

    申请日:2015-06-10

    CPC classification number: H01L22/12 H01L22/20

    Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.

    Air gap formation in interconnection structure by implantation process
    62.
    发明授权
    Air gap formation in interconnection structure by implantation process 有权
    通过植入工艺在互连结构中形成气隙

    公开(公告)号:US09595467B2

    公开(公告)日:2017-03-14

    申请号:US14597149

    申请日:2015-01-14

    Abstract: Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.

    Abstract translation: 提供了使用离子注入工艺形成在互连结构的不同位置上形成的所需材料的互连结构中的空气间隙以限定蚀刻边界,然后进行半导体器件的蚀刻工艺的方法。 在一个实施例中,一种用于在衬底上形成互连结构中的气隙的方法,所述方法包括将离子注入设置在衬底上的绝缘材料的第一区域中,留下没有注入离子的第二区域,第二区域具有第一 与第一区域接合的表面和与衬底接合的第二表面,以及执行蚀刻工艺以选择性地蚀刻第二区域远离衬底,在第一区域和衬底之间形成气隙。

    Plasma process chambers employing distribution grids having focusing surfaces thereon enabling angled fluxes to reach a substrate, and related methods
    63.
    发明授权
    Plasma process chambers employing distribution grids having focusing surfaces thereon enabling angled fluxes to reach a substrate, and related methods 有权
    等离子体处理室采用其上具有聚焦表面的分配网格,能够使角度通量到达基板,以及相关方法

    公开(公告)号:US09534289B2

    公开(公告)日:2017-01-03

    申请号:US14657405

    申请日:2015-03-13

    Abstract: Plasma process chambers employing distribution grids having focusing surfaces thereon enabling angled fluxes to reach a substrate, and associated methods are disclosed. A distribution grid is disposed in a chamber between the plasma and a substrate. The distribution grid includes a first surface facing the substrate and a focusing surface facing the plasma. A passageway extends through the distribution grid, and is sized with a width to prevent the plasma sheath from entering therein. By positioning the focusing surface at an angle other than parallel to the substrate, an ion flux from the plasma may be accelerated across the plasma sheath and particles of the flux pass through the passageway to be incident upon the substrate. In this manner, the angled ion flux may perform thin film deposition and etch processes on sidewalls of features extending orthogonally from or into the substrate, as well as angled implant and surface modification.

    Abstract translation: 等离子体处理室采用其上具有聚焦表面的分配网格,其上形成有角度的焊剂以到达衬底,以及相关方法。 配电网布置在等离子体和基板之间的室中。 配电网包括面向衬底的第一表面和面向等离子体的聚焦表面。 通道延伸穿过配电网,并且具有宽度的尺寸以防止等离子体护套进入其中。 通过将聚焦表面定位在与衬底不同的角度处,来自等离子体的离子通量可以跨越等离子体鞘加速,并且助焊剂的颗粒通过通道入射到衬底上。 以这种方式,成角度的离子通量可以在从基底垂直延伸的特征的侧壁上进行薄膜沉积和蚀刻处理,以及成角度的植入物和表面改性。

    Anisotropic gap etch
    64.
    发明授权
    Anisotropic gap etch 有权
    各向异性间隙蚀刻

    公开(公告)号:US09502258B2

    公开(公告)日:2016-11-22

    申请号:US14581332

    申请日:2014-12-23

    Abstract: A method of anisotropically dry-etching exposed substrate material on a patterned substrate is described. The patterned substrate has a gap formed in a single material made from, for example, a silicon-containing material or a metal-containing material. The method includes directionally ion-implanting the patterned structure to implant the bottom of the gap without implanting substantially the walls of the gap. Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that either (1) the walls are selectively etched relative to the floor of the gap, or (2) the floor is selectively etched relative to the walls of the gap. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.

    Abstract translation: 描述了在图案化衬底上各向异性地干蚀刻暴露的衬底材料的方法。 图案化衬底具有由例如含硅材料或含金属材料制成的单一材料形成的间隙。 该方法包括定向离子注入图案化结构以植入间隙的底部,而基本上不插入间隙的壁。 随后,使用含氟前体形成远程等离子体以蚀刻图案化衬底,使得(1)相对于间隙的底板选择性地蚀刻壁,或者(2)相对于壁选择性地蚀刻地板 的差距。 在没有离子注入的情况下,蚀刻操作将是各向同性的,这是由于在蚀刻过程期间等离子体激发的远程特性。

    Field guided exposure and post-exposure bake process
    66.
    发明授权
    Field guided exposure and post-exposure bake process 有权
    现场指导曝光和曝光后烘烤过程

    公开(公告)号:US09280070B2

    公开(公告)日:2016-03-08

    申请号:US14476944

    申请日:2014-09-04

    CPC classification number: G03F7/38 G03F7/2022 G03F7/70325

    Abstract: Methods disclosed herein apply an electric field and/or a magnetic field during photolithography processes. The field application may control the diffusion of the charged species generated by the photoacid generator along the line and spacing direction, preventing the line edge/width roughness that results from random diffusion. The field application may additionally or alternatively control the diffusion of the charged species in a direction perpendicular to a plane formed by the photoresist layer. Such controlled perpendicular diffusion may increase the photoresist sensitivity. In other embodiments, the field may control the diffusion of the charged species within the plane of the photoresist layer but in a direction perpendicular or non-parallel to the line and spacing direction. Apparatuses for carrying out the aforementioned methods are also disclosed herein.

    Abstract translation: 本文公开的方法在光刻工艺期间施加电场和/或磁场。 场应用可以控制由光致酸发生器沿着线和间隔方向产生的带电物质的扩散,从而防止由随机扩散引起的线边缘/宽度粗糙度。 场应用可以附加地或替代地控制带电物质在垂直于由光致抗蚀剂层形成的平面的方向上的扩散。 这种受控的垂直扩散可以增加光致抗蚀剂的灵敏度。 在其他实施例中,场可以控制带电物质在光致抗蚀剂层的平面内但在垂直于或不平行于线和间隔方向的方向上的扩散。 用于实施上述方法的装置也在此公开。

    Methods for silicon recess structures in a substrate by utilizing a doping layer
    67.
    发明授权
    Methods for silicon recess structures in a substrate by utilizing a doping layer 有权
    通过利用掺杂层在衬底中的硅凹陷结构的方法

    公开(公告)号:US09214377B2

    公开(公告)日:2015-12-15

    申请号:US14068312

    申请日:2013-10-31

    Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

    Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法,特别适用于制造用于半导体芯片的鳍式场效应晶体管(FinFET)的三维(3D)堆叠。 在一个实施例中,在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分,直到形成在衬底中的掺杂层露出。

    Optical device improvement
    68.
    发明授权

    公开(公告)号:US12249489B2

    公开(公告)日:2025-03-11

    申请号:US18131997

    申请日:2023-04-07

    Abstract: A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.

    Optical resolution measurement method for optical devices

    公开(公告)号:US12165341B2

    公开(公告)日:2024-12-10

    申请号:US17534167

    申请日:2021-11-23

    Abstract: Embodiments herein provide for a method of determining an optical device modulation transfer function (MTF). The method described herein includes projecting a baseline image of a pattern from a light engine to a detector. The baseline image is analyzed to determine a baseline function. A baseline fast Fourier transform (FFT) or a baseline MTF of the baseline function is obtained. The method further includes projecting an image of the pattern from the light engine to one or more optical devices. The pattern is outcoupled from the one or more optical devices to the detector. The image is analyzed to determine a function. A function FFT or a function MTF is obtained corresponding to the image. An optical device MTF of the one or more optical devices is determined by comparing the baseline FFT and the function FFT determined by analyzing the image or by comparing the baseline MTF and the function MTF determined by analyzing the image.

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