公开(公告)号：US11959167B2

公开(公告)日：2024-04-16

申请号：US17834633

申请日：2022-06-07

Applicant: Applied Materials, Inc.

Inventor： Sang-Ho Yu ,  Kevin Moraes ,  Seshadri Ganguli ,  Hua Chung ,  See-Eng Phan

IPC: C23C16/16 ,  C23C16/02 ,  C23C16/18 ,  C23C16/455 ,  C23C16/50 ,  H01L21/02 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768

CPC classification number: C23C16/16 ,  C23C16/0218 ,  C23C16/0245 ,  C23C16/18 ,  C23C16/4554 ,  C23C16/45542 ,  C23C16/50 ,  H01L21/02068 ,  H01L21/02074 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/324 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76883

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers.

公开(公告)号：US11946135B2

公开(公告)日：2024-04-02

申请号：US18190246

申请日：2023-03-27

Applicant: Applied Materials, Inc.

Inventor： Feng Q. Liu ,  Hua Chung ,  Schubert Chu ,  Mei Chang ,  Jeffrey W. Anthis ,  David Thompson

IPC: C23C16/42 ,  C23C16/14 ,  C23C16/455 ,  C23C16/507 ,  C23C16/513 ,  C23C16/52

CPC classification number: C23C16/42 ,  C23C16/14 ,  C23C16/45536 ,  C23C16/45542 ,  C23C16/507 ,  C23C16/513 ,  C23C16/52

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

公开(公告)号：US11018003B2

公开(公告)日：2021-05-25

申请号：US16513301

申请日：2019-07-16

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Hua Chung

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: In an embodiment, a method of selectively depositing a silicon germanium material on a substrate is provided. The method includes positioning the substrate within a substrate processing chamber, the substrate having a dielectric material and a silicon containing single crystal thereon; maintaining the substrate at a temperature of about 450° C. or less; exposing the substrate to a process gas comprising: a silicon source gas, a germanium source gas, an etchant gas, a carrier gas, and at least one dopant source gas; and epitaxially and selectively depositing a first silicon germanium material on the substrate.

公开(公告)号：US20190078203A1

公开(公告)日：2019-03-14

申请号：US16129232

申请日：2018-09-12

Applicant: Applied Materials, Inc.

Inventor： Feng Q. Liu ,  Hua Chung ,  Schubert Chu ,  Mei Chang ,  Jeffrey W. Anthis ,  David Thompson

IPC: C23C16/42 ,  C23C16/52 ,  C23C16/455 ,  C23C16/513

Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

公开(公告)号：US10090147B2

公开(公告)日：2018-10-02

申请号：US15890117

申请日：2018-02-06

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Melitta Manyin Hon ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02 ,  H01L29/66

Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

公开(公告)号：US10043667B2

公开(公告)日：2018-08-07

申请号：US15418190

申请日：2017-01-27

Applicant: Applied Materials, Inc.

Inventor： Chun Yan ,  Xinyu Bao ,  Hua Chung ,  Schubert S. Chu

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/08 ,  C23C14/58 ,  H01L21/20 ,  C23C14/02 ,  H01L21/768 ,  H01L21/203

Abstract: Implementations disclosed herein relate to methods for controlling substrate outgassing. In one implementation, the method includes removing oxides from an exposed surface of a substrate in an inductively coupled plasma chamber, forming an epitaxial layer on the exposed surface of the substrate in an epitaxial deposition chamber, and performing an outgassing control of the substrate by subjecting the substrate to a first plasma formed from a first etch precursor in the inductively coupled plasma chamber at a first chamber pressure, wherein the first etch precursor comprises a hydrogen-containing precursor, a chlorine-containing precursor, and an inert gas, and subjecting the substrate to a second plasma formed from a second etch precursor in the inductively coupled plasma chamber at a second chamber pressure that is higher than the first chamber pressure, wherein the second etch precursor comprises a hydrogen-containing precursor and an inert gas.

公开(公告)号：US09932670B2

公开(公告)日：2018-04-03

申请号：US14149526

申请日：2014-01-07

Applicant: Applied Materials, Inc.

Inventor： Jie Su ,  Lori D. Washington ,  Sandeep Nijhawan ,  Olga Kryliouk ,  Jacob Grayson ,  Sang Won Kang ,  Dong Hyung Lee ,  Hua Chung

IPC: B08B9/00 ,  B08B5/00 ,  C23C16/44 ,  C23C16/455 ,  H01L21/67

CPC classification number: C23C16/4405 ,  C23C16/4404 ,  C23C16/45574 ,  H01L21/67115

Abstract: A method and apparatus for removing deposition products from internal surfaces of a processing chamber, and for preventing or slowing growth of such deposition products. A halogen containing gas is provided to the chamber to etch away deposition products. A halogen scavenging gas is provided to the chamber to remove any residual halogen. The halogen scavenging gas is generally activated by exposure to electromagnetic energy, either inside the processing chamber by thermal energy, or in a remote chamber by electric field, UV, or microwave. A deposition precursor may be added to the halogen scavenging gas to form a deposition resistant film on the internal surfaces of the chamber. Additionally, or alternately, a deposition resistant film may be formed by sputtering a deposition resistant metal onto internal components of the processing chamber in a PVD process.

公开(公告)号：US09419107B2

公开(公告)日：2016-08-16

申请号：US14320590

申请日：2014-06-30

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L29/00 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/161 ,  H01L21/265 ,  H01L21/324 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/775

CPC classification number: H01L29/66795 ,  B82Y10/00 ,  B82Y40/00 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02359 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/265 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66666 ,  H01L29/775

Abstract: Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes performing an ion implantation process to dope dopants into a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer predominantly comprises a first type of atoms formed therein, the dopants including a second type of atoms into the suspended nanowire structure, oxidating surfaces of the multiple material layers, and converting the first type of atoms in the material layer to the second type of atoms from the dopants doped therein.

Abstract translation: 本公开的实施例提供了用于形成用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的所需材料的纳米线结构的方法。 在一个实例中，在衬底上形成纳米线结构的方法包括进行离子注入工艺以将掺杂剂掺杂到衬底上的悬浮的纳米线结构中，所述悬浮的纳米线包括在悬浮的纳米线结构中重复形成间隔关系的多个材料层 ，其中所述材料层主要包含在其中形成的第一类型的原子，所述掺杂剂包括到所述悬浮的纳米线结构中的第二类型的原子，所述多个材料层的氧化表面，以及将所述材料层中的所述第一类型的原子转化为 来自掺杂掺杂物的第二类型的原子。

公开(公告)号：US09412603B2

公开(公告)日：2016-08-09

申请号：US14548044

申请日：2014-11-19

Applicant: Applied Materials, Inc.

Inventor： Ying Zhang ,  Hua Chung

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/30604 ,  H01L21/02126 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66818

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract translation: 本文描述的实施例通常涉及形成次10nm节点FinFET的方法。 在基板上执行各种处理步骤，以提供限定心轴结构的沟槽。 心轴结构的侧壁和沟槽的底表面被氧化并随后被蚀刻以减小心轴结构的宽度。 可以重复心轴结构的氧化和蚀刻，直到实现心轴结构的期望宽度。 随后将半导体材料沉积在心轴结构的再生长区域上以形成翅片结构。 氧化和蚀刻心轴结构提供了一种用于形成翅片结构的方法，其可实现10nm以下的节点尺寸并提供越来越小的FinFET。

公开(公告)号：US09214377B2

公开(公告)日：2015-12-15

申请号：US14068312

申请日：2013-10-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Ying Zhang ,  Hua Chung ,  Srinivas D. Nemani ,  Ludovic Godet

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/265

CPC classification number: H01L21/76224 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/6831 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠。 在一个实施例中，在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分，直到形成在衬底中的掺杂层露出。