公开(公告)号：US20090159991A1

公开(公告)日：2009-06-25

申请号：US11960881

申请日：2007-12-20

申请人： Bernd Ernst Eduard Kastenmeier ,  Byoung Hun Lee ,  Naim Moumen ,  Theodorus Eduardus Standaert

发明人： Bernd Ernst Eduard Kastenmeier ,  Byoung Hun Lee ,  Naim Moumen ,  Theodorus Eduardus Standaert

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L27/092

摘要： A semiconductor structure and a method of forming the same. The semiconductor structure includes a semiconductor substrate, a gate dielectric layer on top of the semiconductor substrate. The structure also includes a first metal containing region on top of the gate dielectric layer. The structure also includes a second metal containing region on top of the gate dielectric layer wherein the first and second metal containing regions are in direct physical contact with each other. The structure further includes a gate electrode layer on top of both the first and second metal containing regions and the gate electrode layer is in direct physical contact with both the first and second metal containing regions. The structure further includes a patterned photoresist layer on top of the gate electrode layer.

摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底，在半导体衬底的顶部上的栅极电介质层。 该结构还包括位于栅介质层顶部的第一金属容纳区域。 该结构还包括在栅极电介质层的顶部上的第二金属容纳区域，其中第一和第二金属容纳区域彼此直接物理接触。 该结构还包括在第一和第二金属容纳区域的顶部上的栅极电极层，并且栅电极层与第一和第二金属容纳区域直接物理接触。 该结构还包括在栅极电极层的顶部上的图案化光致抗蚀剂层。

公开(公告)号：US20090152636A1

公开(公告)日：2009-06-18

申请号：US11954749

申请日：2007-12-12

申请人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

发明人： Michael P. Chudzik ,  Naim Moumen ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.

摘要翻译： 公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。 在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

公开(公告)号：US20070296947A1

公开(公告)日：2007-12-27

申请号：US11899085

申请日：2007-09-04

申请人： Steven Holmes ,  Toshiharu Furukawa ,  Charles Koburger ,  Naim Moumen

发明人： Steven Holmes ,  Toshiharu Furukawa ,  Charles Koburger ,  Naim Moumen

IPC分类号： G03B27/42

CPC分类号： G03F7/2041 ,  G03F7/11 ,  G03F7/70341 ,  G03F7/70958

摘要： An immersion lithography system is provided which includes an optical source operable to produce light having a nominal wavelength and an optical imaging system. The optical imaging system has an optical element in an optical path from the optical source to an article to be patterned thereby. The optical element has a face which is adapted to contact a liquid occupying a space between the face and the article. The optical element includes a material which is degradable by the liquid and a protective coating which covers the degradable material at the face for protecting the face from the liquid, the protective coating being transparent to the light, stable when exposed to the light and stable when exposed to the liquid.

摘要翻译： 提供了一种浸没光刻系统，其包括可操作以产生具有标称波长的光和光学成像系统的光源。 光学成像系统具有从光源到待图案化的制品的光路中的光学元件。 光学元件具有适于接触占据面部和制品之间的空间的液体的面。 光学元件包括可被液体降解的材料和覆盖面上的可降解材料以保护面部免受液体的保护涂层，保护涂层对于光是透明的，当暴露于光时稳定，并且当稳定时 暴露于液体。

公开(公告)号：US20070048920A1

公开(公告)日：2007-03-01

申请号：US11212127

申请日：2005-08-25

申请人： Seung-Chul Song ,  Zhibo Zhang ,  Byoung Lee ,  Naim Moumen ,  Joel Barnett ,  Muhammad Hussain ,  Rino Choi ,  Husam Alshareef

发明人： Seung-Chul Song ,  Zhibo Zhang ,  Byoung Lee ,  Naim Moumen ,  Joel Barnett ,  Muhammad Hussain ,  Rino Choi ,  Husam Alshareef

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823842

摘要： Methods for fabricating two metal gate stacks for complementary metal oxide semiconductor (CMOS) devices are provided. A first metal layer may be deposited onto a gate dielectric. Next a mask layer may be deposited on the first metal layer and subsequently etch. The first metal layer is then etched. Without removing the mask layer, a second metal layer may be deposited. In one embodiment, the mask layer is a second metal layer. In other embodiments, the mask layer is a silicon layer. Subsequent fabrication steps include depositing another metal layer (e.g., another PMOS metal layer), depositing a cap, etching the cap to define gate stacks, and simultaneously etching the first and second gate region having a similar thickness with differing metal layers.

摘要翻译： 提供了用于制造用于互补金属氧化物半导体（CMOS）器件的两个金属栅极叠层的方法。 可以将第一金属层沉积到栅极电介质上。 接下来，掩模层可以沉积在第一金属层上并随后蚀刻。 然后蚀刻第一金属层。 在不去除掩模层的情况下，可沉积第二金属层。 在一个实施例中，掩模层是第二金属层。 在其他实施例中，掩模层是硅层。 随后的制造步骤包括沉积另一金属层（例如，另一个PMOS金属层），沉积帽，蚀刻帽以限定栅极堆叠，以及同时用不同的金属层蚀刻具有相似厚度的第一和第二栅极区域。

公开(公告)号：US07129564B2

公开(公告)日：2006-10-31

申请号：US11059819

申请日：2005-02-17

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Shane Wrschka

IPC分类号： H01L31/117

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

摘要翻译： 本文公开的形成缺口栅极MOSFET的结构和方法解决了诸如器件可靠性的问题。 栅电介质（例如栅极氧化物）形成在半导体衬底上的有源区的表面上，优选由隔离沟槽区限定。 然后在栅极电介质上沉积多晶硅层。 该步骤之后是沉积一层硅锗）（SiGe）。 然后横向蚀刻多晶硅层的侧壁，对SiGe层有选择性，以产生刻蚀的栅极导体结构，其中SiGe层比下面的多晶硅层宽。 侧壁间隔物优选形成在SiGe层和多晶硅层的侧壁上。 硅化物层优选从沉积在SiGe层上的多晶硅层形成为自对准硅化物，以降低栅极导体的电阻。 优选在完成晶体管时执行一个或多个其它处理步骤（例如源极和漏极注入，延伸注入和袖带轻掺杂漏极（LDD）注入），栅极导体堆叠掺杂和硅化。

公开(公告)号：US20060115937A1

公开(公告)日：2006-06-01

申请号：US11324934

申请日：2006-01-04

申请人： Joel Barnett ,  Mark Gardner ,  Naim Moumen ,  Jim Gutt

发明人： Joel Barnett ,  Mark Gardner ,  Naim Moumen ,  Jim Gutt

IPC分类号： H01L21/84 ,  H01L21/31 ,  H01L21/302

CPC分类号： H01L21/02337 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

摘要： Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.

摘要翻译： 描述了用于高k材料和硅之间的绝缘电介质界面的方法和装置，以改善器件的电特性。 一种方法包括使用原位蒸汽产生工艺在硅衬底上形成氧化物层，蚀刻氧化物层以形成小于10埃的厚度减小的氧化物层，并且用氨将还原厚度的氧化物层退火。 半导体晶片包括硅衬底，耦合到硅衬底的氧化物层，其中氧化物层具有小于10埃的厚度，以及沉积在氧化物层上的高k电介质材料。

公开(公告)号：US20060081830A1

公开(公告)日：2006-04-20

申请号：US10965370

申请日：2004-10-14

申请人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

发明人： Andreas Knorr ,  Bernd Kastenmeier ,  Naim Moumen

IPC分类号： H01L29/04

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming air gaps or porous dielectric materials between interconnects of integrated circuits and structures thereof. Air gaps or highly porous dielectric material having a dielectric constant of close to or equal to 1.0 are formed in a first region but not a second region of an interconnect layer. The air gaps or highly porous dielectric material are formed by depositing a first insulating material comprising an energy-sensitive material over a workpiece, depositing a second insulating material over the first insulating material, and exposing the workpiece to energy. At least a portion of the first insulating material in the first region is removed through the second insulating material. Structurally stable insulating material is disposed between conductive lines in the second region of the workpiece, providing mechanical strength for the integrated circuit.

公开(公告)号：US06987042B2

公开(公告)日：2006-01-17

申请号：US10250046

申请日：2003-05-30

申请人： Jochen Beintner ,  Naim Moumen ,  Porshia S. Wrschka

发明人： Jochen Beintner ,  Naim Moumen ,  Porshia S. Wrschka

IPC分类号： H01L21/8242

CPC分类号： H01L27/1087 ,  H01L21/30604 ,  H01L29/66181 ,  H01L29/945

摘要： A method of forming collar isolation for a trench storage memory cell structure is provided in which amorphous Si (a:Si) and silicon germanium (SiGe) are first formed into a trench structure. An etching process that is selective to a:Si as compared to SiGe is employed in defining the regions in which the collar isolation will be formed. The selective etching process employed in the present invention is a wet etch process that includes etching with HF, rinsing, etching with NH4OH, rinsing, and drying with a monohydric alcohol such as isopropanol. The sequence of NH4OH etching and rinsing may be repeated any number of times. The conditions used in the selective etching process of the present invention are capable of etching a:Si at a faster rate than SiGe.

摘要翻译： 提供了一种形成沟槽存储单元结构的套环隔离的方法，其中首先将非晶硅（a：Si）和硅锗（SiGe）形成沟槽结构。 与SiGe相比，对a：Si有选择性的蚀刻工艺用于限定将形成套环隔离的区域。 在本发明中采用的选择性蚀刻方法是湿式蚀刻工艺，其包括用HF蚀刻，漂洗，用NH 4 OH蚀刻，漂洗和用一元醇如异丙醇干燥。 NH 4 OH蚀刻和漂洗的顺序可以重复任意次数。 在本发明的选择性蚀刻工艺中使用的条件能够以比SiGe更快的速度蚀刻Si。

公开(公告)号：US20050158927A1

公开(公告)日：2005-07-21

申请号：US11059819

申请日：2005-02-17

申请人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Wrschka

发明人： Jochen Beintner ,  Yujun Li ,  Naim Moumen ,  Porshia Wrschka

IPC分类号： H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/28044 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/665 ,  Y10S438/933

摘要： The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g. source and drain implants, extension implants, and pocket lightly doped drain (LDD) implants), gate conductor stack doping, and silicidation are preferably performed in completing the transistor.

公开(公告)号：US20050070120A1

公开(公告)日：2005-03-31

申请号：US10911981

申请日：2004-08-05

申请人： Joel Barnett ,  Mark Gardner ,  Naim Moumen ,  Jim Gutt

发明人： Joel Barnett ,  Mark Gardner ,  Naim Moumen ,  Jim Gutt

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/02337 ,  H01L21/02142 ,  H01L21/02148 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659

摘要： Methods and devices are described for an insulated dielectric interface between a high-k material and silicon for improving electrical characteristics of devices. A method includes forming an oxide layer on a silicon substrate using an in situ steam generation process, etching the oxide layer to form a reduced thickness oxide layer of less than 10 Angstroms, and annealing the reduced thickness oxide layer with ammonia. A semiconductor wafer comprises a silicon substrate, an oxide layer coupled to the silicon substrate where the oxide layer having a thickness of less than 10 Angstroms, and a high-k dielectric material deposited onto the oxide layer.

摘要翻译： 描述了用于高k材料和硅之间的绝缘电介质界面的方法和装置，以改善器件的电特性。 一种方法包括使用原位蒸汽产生工艺在硅衬底上形成氧化物层，蚀刻氧化物层以形成小于10埃的厚度减小的氧化物层，并且用氨将还原厚度的氧化物层退火。 半导体晶片包括硅衬底，耦合到硅衬底的氧化物层，其中氧化物层具有小于10埃的厚度，以及沉积在氧化物层上的高k电介质材料。