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104 条记录 (耗时 0.047 秒)

    Apparatus for sharing sense amplifiers between memory banks
    62.
    发明授权
    Apparatus for sharing sense amplifiers between memory banks 失效
    用于在存储体之间共享读出放大器的装置

    公开(公告)号：US06134172A

    公开(公告)日：2000-10-17

    申请号：US862641

    申请日：1997-05-23

    申请人： Richard M. Barth ,  Donald C. Stark ,  Ely K. Tsern

    发明人： Richard M. Barth ,  Donald C. Stark ,  Ely K. Tsern

    IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/00 ,  G11C11/409 ,  G11C7/06

    摘要： A memory device includes a first memory bank and a second memory bank, each memory bank having at least one subarray of memory cells. Multiple sense amplifiers are coupled to at least one subarray of memory cells. At least one sense amplifier is configured for use by both the first memory bank and the second memory bank, but not simultaneously. The sharing of sense amplifiers between memory banks minimizes the die area penalty caused by additional memory banks. The memory device is configured such that the first memory bank is adjacent to the second memory bank.

    摘要翻译： 存储器件包括第一存储体和第二存储体，每个存储体具有至少一个存储单元的子阵列。 多个读出放大器耦合到存储器单元的至少一个子阵列。 至少一个读出放大器被配置为由第一存储体和第二存储体使用，但不能同时使用。 存储器组之间的读出放大器的共享使由附加存储体引起的管芯面积损失最小化。 存储器件被配置为使得第一存储体与第二存储体相邻。

    Memory and method for sensing sub-groups of memory elements
    65.
    发明授权
    Memory and method for sensing sub-groups of memory elements 失效
    用于感测存储器元件子组的存储器和方法

    公开(公告)号：US5748554A

    公开(公告)日：1998-05-05

    申请号：US771303

    申请日：1996-12-20

    申请人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

    发明人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

    IPC分类号： G11C7/06 ,  G11C8/14 ,  G11C11/408 ,  G11C11/4091 ,  B11C13/00

    CPC分类号： G11C7/06 ,  G11C11/4085 ,  G11C11/4091 ,  G11C8/14

    摘要： A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.

    摘要翻译： 描述了存储器和操作方法。 在一个实施例中，存储器包括分成多个子组的一组存储器单元。 子字线选择性地耦合到主字线，每个子字线对应于子组，并且被耦合到相应子组的行中的存储器单元。 感测放大器电路耦合到该组存储器单元。 感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中对应的一个子组。 存储器包括一个控制机制，用于控制在任何一个时间被激活的字线和子感测电路，使得只需要执行存储器操作所需的那些子字线和子感测电路并消耗功率。 在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

    Memory and method for sensing sub-groups of memory elements
    66.
    再颁专利
    Memory and method for sensing sub-groups of memory elements 有权
    用于感测存储器元件子组的存储器和方法

    公开(公告)号：USRE37409E1

    公开(公告)日：2001-10-16

    申请号：US09559836

    申请日：2000-04-26

    申请人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

    发明人： Richard M. Barth ,  Donald C. Stark ,  Lawrence Lai ,  Wayne S. Richardson

    IPC分类号： G11C1300

    CPC分类号： G11C7/06 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4091

    摘要： A memory and method of operation is disclosed. In one embodiment, the memory includes a group of memory cells divided into a plurality of subgroups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a subgroup and is coupled to the memory cells in the row of the corresponding subgroup. Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit (s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.

    摘要翻译： 公开了一种存储器和操作方法。 在一个实施例中，存储器包括分成多个子组的一组存储器单元。 子字线选择性地耦合到主字线，每个子字线对应于一个子组，并且被耦合到相应子组的行中的存储器单元。 感测放大器电路耦合到该组存储器单元。 感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中对应的一个子组。 存储器包括一个控制机构，用于控制在任何一个时间被激活的字线和子感应电路，使得只需要执行存储器操作所需的子字线和子感测电路并消耗功率。 在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

    Multiple sweep point testing of circuit devices
    69.
    发明授权
    Multiple sweep point testing of circuit devices 失效
    电路设备的多次扫描点测试

    公开(公告)号：US07331006B2

    公开(公告)日：2008-02-12

    申请号：US11201609

    申请日：2005-08-10

    申请人： Timothy C. Chang ,  Donald C. Stark

    发明人： Timothy C. Chang ,  Donald C. Stark

    IPC分类号： G01R31/3183 ,  G01R31/40

    CPC分类号： G01R31/31919 ,  G01R31/31935

    摘要： An efficient method and apparatus for characterizing circuit devices is disclosed. In one embodiment, multiple test patterns for testing a circuit device are stored in a tester. Each test pattern includes both test data and control data that defines at least in part a sweep point at which the circuit device is tested. Thus, the tester can generate stimulus vectors for multiple sweep points without requiring control system intervention. Pass/fail indicators, each of which represents pass/fail results associated with a sweep point, are derived from the test results and stored in a Fail Capture Memory. A pass/fail boundary of the DUT can be determined from the contents of the Fail Capture Memory.

    摘要翻译： 公开了一种用于表征电路装置的有效方法和装置。 在一个实施例中，用于测试电路设备的多个测试图案被存储在测试器中。 每个测试模式包括测试数据和至少部分地定义电路设备被测试的扫描点的控制数据。 因此，测试者可以产生多个扫描点的刺激向量，而不需要控制系统干预。 通过/失败指示器，每个都表示与扫描点相关联的通过/失败结果，从测试结果中导出并存储在故障捕获内存中。 DUT的通过/失败边界可以根据故障捕获存储器的内容来确定。

    Delay locked loop circuitry for clock delay adjustment
    70.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H04L700

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。