公开(公告)号：US10229855B2

公开(公告)日：2019-03-12

申请号：US15846365

申请日：2017-12-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66

Abstract: A device includes a first transistor device having a first threshold voltage and including a first gate electrode structure positioned in a first gate cavity. The first gate electrode structure includes a first gate insulation layer, a first barrier layer, a first work function material layer formed above the first barrier layer, a second barrier layer formed above the first work function material layer, and a first conductive material formed above the second barrier layer. A second transistor device has a second threshold voltage different than the first threshold voltage and includes a second gate electrode structure positioned in a second cavity defined in the dielectric layer. The second gate electrode structure includes a second gate insulation layer, a second work function material layer, the second barrier layer formed above the second work function material layer, and a second conductive material formed above the second barrier layer.

公开(公告)号：US10199264B2

公开(公告)日：2019-02-05

申请号：US15875212

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Roderick A. Augur ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

公开(公告)号：US10038065B2

公开(公告)日：2018-07-31

申请号：US15639095

申请日：2017-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Min Gyu Sung ,  Hoon Kim

IPC: H01L29/417 ,  H01L29/41 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L29/41775 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed includes, among other things, forming an initial conductive source/drain structure that is conductively coupled to a source/drain region of a transistor device, performing a recess etching process on the initial conductive source/drain structure to thereby define a stepped conductive source/drain structure with a cavity defined therein, forming a non-conductive structure in the cavity, forming a layer of insulating material above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, forming a gate contact opening in the layer of insulating material and forming a conductive gate contact in the gate contact opening that is conductively coupled to the gate structure.

公开(公告)号：US10026655B2

公开(公告)日：2018-07-17

申请号：US15647453

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

Abstract: An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.

公开(公告)号：US10014209B2

公开(公告)日：2018-07-03

申请号：US15630546

申请日：2017-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Sukwon Hong

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

公开(公告)号：US20180061832A1

公开(公告)日：2018-03-01

申请号：US15801023

申请日：2017-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie ,  Kwan-Yong Lim

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level. The first oxide recess level is within a predetermined height differential of the second oxide recess level.

公开(公告)号：US09875940B2

公开(公告)日：2018-01-23

申请号：US14820701

申请日：2015-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hoon Kim ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L21/82345 ,  H01L21/02181 ,  H01L21/28088 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method includes forming first and second gate cavities so as to expose first and second portions of a semiconductor material. A gate insulation layer is formed in the first and second gate cavities. A first work function material layer is formed in the first gate cavity. A second work function material layer is formed in the second gate cavity. A first barrier layer is selectively formed above the first work function material layer and the gate insulation layer in the first gate cavity. A second barrier layer is formed above the first barrier layer in the first gate cavity and above the second work function material layer and the gate insulation layer in the second gate cavity. A conductive material is formed above the second barrier layer in the first and second gate cavities in the presence of a treatment species to define first and second gate electrode structures.

公开(公告)号：US09831132B2

公开(公告)日：2017-11-28

申请号：US15645395

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US09824920B2

公开(公告)日：2017-11-21

申请号：US15089834

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49 ,  H01L23/535

CPC classification number: H01L21/76897 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.

公开(公告)号：US09761495B1

公开(公告)日：2017-09-12

申请号：US15050540

申请日：2016-02-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Catherine B. Labelle ,  Chanro Park ,  Hoon Kim

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is formed above the plurality of fins and the plurality of gate structures. The first mask layer has at least one fin cut opening and at least one gate cut opening defined therein. A first portion of a first fin of the plurality of fins disposed below the fin cut opening is removed to define a fin cut cavity. A second portion of a first gate structure of the plurality of gate structures disposed below the gate cut opening is removed to define a gate cut cavity. An insulating material layer is concurrently formed in at least a portion of the fin cut cavity and the gate cut cavity.