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    METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE
    61.
    发明申请
    METHODS OF INDUCING A DESIRED STRESS IN THE CHANNEL REGION OF A TRANSISTOR BY PERFORMING ION IMPLANTATION/ANNEAL PROCESSES ON THE GATE ELECTRODE 有权
    通过对栅极电极进行离子植入/阳极处理，在晶体管的通道区域中诱导所需应力的方法

    公开(公告)号：US20140231907A1

    公开(公告)日：2014-08-21

    申请号：US13771294

    申请日：2013-02-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ralf Richter ,  Peter Javorka ,  Stefan Flachowsky ,  Nicolas Sassiat

    IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

    CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/7847

    Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

    Abstract translation: 这里的一种方法包括在半导体衬底的有源区上方形成栅极结构，形成与栅极结构相邻的侧壁间隔结构，形成允许将离子注入栅电极但不进入有源区的源的/ 将形成用于晶体管的漏极区域，执行栅极离子注入工艺以在栅极电极中形成栅极离子注入区域并执行退火工艺。 一种N型晶体管，其包括邻近栅极结构定位的侧壁间隔结构，用于晶体管的多个源极/漏极区域和位于栅极电极中的栅极注入区域，其中栅极注入区域由磷，砷或 原子尺寸等于或大于磷离子浓度在5e18-5e21离子/ cm3范围内的原子尺寸的植入材料。

    METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS
    62.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING GATE TO ACTIVE AND GATE TO GATE INTERCONNECTS 有权
    用于制造具有门到集成电路的主动和门来互连的方法

    公开(公告)号：US20140220759A1

    公开(公告)日：2014-08-07

    申请号：US14244611

    申请日：2014-04-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

    IPC: H01L29/66 ,  H01L21/762

    CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

    Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

    Abstract translation: 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括形成虚拟栅极结构，其包括具有侧壁并覆盖半导体衬底的伪栅极电极以及虚设栅电极的侧壁上的第一和第二侧壁间隔物。 该方法包括去除伪栅电极以形成由第一和第二侧壁间隔物限定的沟槽。 该方法移除第一侧壁间隔物的上部，并将一层金属沉积在沟槽中并在第一侧壁间隔物的剩余部分上方形成栅电极和互连。

    SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE
    63.
    发明申请
    SEMICONDUCTOR DEVICE WITH A SILICON DIOXIDE GATE INSULATION LAYER IMPLANTED WITH A RARE EARTH ELEMENT AND METHODS OF MAKING SUCH A DEVICE 审中-公开
    具有二氧化硅栅绝缘层的半导体器件，其具有稀土元素和制造这种器件的方法

    公开(公告)号：US20140151818A1

    公开(公告)日：2014-06-05

    申请号：US13689936

    申请日：2012-11-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Jan Hoentschel ,  Stefan Flachowsky

    IPC: H01L21/28 ,  H01L29/78

    CPC classification number: H01L21/265 ,  H01L21/28167 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7833

    Abstract: One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative device disclosed herein includes a gate insulation layer positioned on a semiconducting substrate, wherein the gate insulation layer is comprised of silicon dioxide and a rare earth element, and a silicon-containing gate electrode positioned on the gate insulation layer.

    Abstract translation: 本文公开的一种示例性方法包括在半导体衬底上形成栅极绝缘层，执行离子注入工艺以将稀土元素注入到栅极绝缘层中，以及在栅极绝缘层上方形成含硅栅电极，该栅极绝缘层包括植入的稀有金属 地球元素 本文公开的一种说明性器件包括位于半导体衬底上的栅极绝缘层，其中栅极绝缘层由二氧化硅和稀土元素组成，并且位于栅极绝缘层上的含硅栅电极。

    THREE-DIMENSIONAL SILICON-BASED TRANSISTOR COMPRISING A HIGH-MOBILITY CHANNEL FORMED BY NON-MASKED EPITAXY
    64.
    发明申请
    THREE-DIMENSIONAL SILICON-BASED TRANSISTOR COMPRISING A HIGH-MOBILITY CHANNEL FORMED BY NON-MASKED EPITAXY 审中-公开
    包含非掩蔽外观形成的高移动通道的三维硅基晶体管

    公开(公告)号：US20140117418A1

    公开(公告)日：2014-05-01

    申请号：US13663941

    申请日：2012-10-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

    Abstract: Three-dimensional transistors may be formed on the basis of high mobility semiconductor materials, which may be provided locally restricted in the channel region by selective epitaxial growth processes without using a mask material for laterally confining the growing of the high mobility semiconductor material. That is, by controlling process parameters of the selective epitaxial growth process, the cross-sectional shape may be adjusted without requiring a mask material, thereby reducing overall process complexity and providing an additional degree of freedom for adjusting the transistor characteristics in terms of threshold voltage, drive current and electrostatic control of the channel region.

    Abstract translation: 可以基于高迁移率半导体材料形成三维晶体管，高迁移率半导体材料可以通过选择性外延生长工艺局部限制在沟道区域中，而不用掩模材料横向地限制高迁移率半导体材料的生长。 也就是说，通过控制选择性外延生长工艺的工艺参数，可以调节横截面形状而不需要掩模材料，从而降低总体工艺复杂性，并提供用于根据阈值电压调整晶体管特性的附加自由度 ，驱动通道区域的电流和静电控制。

    METHOD INCLUDING A FORMATION OF A TRANSISTOR AND SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR
    67.
    发明申请
    METHOD INCLUDING A FORMATION OF A TRANSISTOR AND SEMICONDUCTOR STRUCTURE INCLUDING A FIRST TRANSISTOR AND A SECOND TRANSISTOR 有权
    包括形成晶体管和半导体结构的方法，包括第一晶体管和第二晶体管

    公开(公告)号：US20170025442A1

    公开(公告)日：2017-01-26

    申请号：US14805827

    申请日：2015-07-22

    Applicant: GLOBALFOUNDRIES Inc

    Inventor： Stefan Flachowsky ,  Ralf Illgen

    IPC: H01L27/12 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L29/66 ,  H01L21/308

    CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

    Abstract: A method includes providing a semiconductor-on-insulator structure including a semiconductor substrate, a layer of electrically insulating material over the semiconductor substrate and a layer of semiconductor material over the layer of electrically insulating material. A first transistor is formed. The formation of the first transistor includes forming a dummy gate structure over the layer of semiconductor material, forming a source region of the first transistor and a drain region of the first transistor in portions of the semiconductor substrate adjacent the dummy gate structure, forming an electrically insulating structure annularly enclosing the dummy gate structure and performing a replacement gate process. The replacement gate process includes removing the dummy gate structure and a portion of the layer of semiconductor material below the dummy gate structure, wherein a recess is formed in the electrically insulating structure. The recess is filled with an electrically conductive material.

    Abstract translation: 一种方法包括提供包括半导体衬底，半导体衬底上的电绝缘材料层和电绝缘材料层上的半导体材料层的绝缘体上半导体结构。 形成第一晶体管。 第一晶体管的形成包括在半导体材料层上形成虚拟栅极结构，在与半栅极结构相邻的半导体衬底的部分中形成第一晶体管的源极区域和第一晶体管的漏极区域，形成电气 绝缘结构环形地包围虚拟栅极结构并执行替换栅极工艺。 替代栅极工艺包括在虚拟栅极结构下方去除伪栅极结构和半导体材料层的一部分，其中在电绝缘结构中形成凹部。 凹部填充有导电材料。

    E-fuse design for high-K metal-gate technology
    69.
    发明授权
    E-fuse design for high-K metal-gate technology 有权
    电子熔丝设计用于高K金属栅极技术

    公开(公告)号：US09515155B2

    公开(公告)日：2016-12-06

    申请号：US14136815

    申请日：2013-12-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

    IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62 ,  H01L23/525

    CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

    Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。

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