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    INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME
    61.
    发明申请
    INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME 有权
    集成电路，包括具有较低接触电阻和降低的PARASIIC电容的FINFET器件及其制造方法

    公开(公告)号：US20140217517A1

    公开(公告)日：2014-08-07

    申请号：US13759156

    申请日：2013-02-05

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

    IPC分类号： H01L27/088 ,  H01L21/28

    CPC分类号： H01L29/7853 ,  H01L21/28 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

    摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

    摘要翻译： 提供了用于制造集成电路的集成电路和方法。 在一个示例中，集成电路包括半导体衬底。 第一翅片和第二翅片彼此相邻，从半导体衬底延伸。 第一翅片具有第一上部，第二翅片具有第二上部。 第一外延部分覆盖第一上部，第二外延部分覆盖第二上部。 第一硅化物层覆盖第一外延部分，第二硅化物层覆盖第二外延部分。 第一和第二硅化物层彼此间隔开以限定横向间隙。 电介质隔离物由电介质材料形成并横跨横向间隙。 接触形成材料覆盖介质间隔物和第一和第二硅化物层的在电介质间隔物的横向上方的部分。

    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
    62.
    发明申请
    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES 有权
    防止半导体器件的腐蚀

    公开(公告)号：US20140124840A1

    公开(公告)日：2014-05-08

    申请号：US13670674

    申请日：2012-11-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    发明人： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/311

    CPC分类号： H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    摘要： A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    摘要翻译： 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    Methods of removing dummy fin structures when forming finFET devices
    63.
    发明授权
    Methods of removing dummy fin structures when forming finFET devices 有权
    在形成finFET器件时去除虚拟鳍片结构的方法

    公开(公告)号：US08703557B1

    公开(公告)日：2014-04-22

    申请号：US13863044

    申请日：2013-04-15

    申请人： GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/6681 ,  H01L21/823821

    摘要： One method disclosed herein includes forming a plurality of fin-formation trenches in a substrate that defines a plurality of fins, wherein at least one of the fins is a dummy fin, forming an insulating material that fills at least a portion of the trenches, forming a recess in a masking layer formed above the insulating material, forming a sidewall spacer on sidewalls of the recess so as to define a spacer opening, performing at least one first etching process on the masking layer through the spacer opening to define an opening in the masking layer that exposes a portion of the insulating material and the dummy fin, and performing at least one second etching process to remove at least a portion of the dummy fin and thereby define an opening in the insulating material.

    摘要翻译： 本文公开的一种方法包括在限定多个翅片的基底中形成多个翅片形成沟槽，其中至少一个翅片是虚拟翅片，形成填充沟槽的至少一部分的绝缘材料，形成 在绝缘材料上形成的掩模层中的凹槽，在凹槽的侧壁上形成侧壁间隔物，以限定间隔开口，通过间隔开口在掩模层上执行至少一个第一蚀刻工艺，以在 暴露绝缘材料和虚拟鳍片的一部分的掩模层，并且执行至少一个第二蚀刻工艺以去除所述虚拟鳍片的至少一部分，从而限定所述绝缘材料中的开口。

    Asymmetric FinFET semiconductor devices and methods for fabricating the same
    70.
    发明授权
    Asymmetric FinFET semiconductor devices and methods for fabricating the same 有权
    非对称FinFET半导体器件及其制造方法

    公开(公告)号：US09583597B2

    公开(公告)日：2017-02-28

    申请号：US13902540

    申请日：2013-05-24

    申请人： GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66795 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/7855

    摘要： Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

    摘要翻译： 提供非对称FinFET器件及其制造方法。 在一个实施例中，一种方法包括提供包括形成在其上的多个翅片结构的半导体衬底，并且在翅片结构上沉积保形衬垫。 去除保形衬套的第一部分，在翅片结构之间留下第一空间，并在翅片结构之间的第一空间中形成第一金属浇口。 去除保形衬套的第二部分，在翅片结构之间留下第二空间，并在翅片结构之间的第二空间中形成第二金属浇口。