公开(公告)号：US20050236679A1

公开(公告)日：2005-10-27

申请号：US11147212

申请日：2005-06-08

申请人： Mitsuaki Hori ,  Hiroyuki Ohta ,  Katsuaki Ookoshi

发明人： Mitsuaki Hori ,  Hiroyuki Ohta ,  Katsuaki Ookoshi

IPC分类号： C23C16/00 ,  C23C16/02 ,  C23C16/34 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L21/022 ,  C23C16/0272 ,  C23C16/345 ,  H01L21/02115 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： A SiO2 film is formed on a semiconductor substrate. Then, a SiN film is formed on the SiO2 film. In this event bis (tertiary butyl amino) silane and NH3 are used as a material gas, and the film forming temperature is set to 600° C. or lower.

公开(公告)号：US20050024811A1

公开(公告)日：2005-02-03

申请号：US10923002

申请日：2004-08-23

申请人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

发明人： Hiroshi Moriya ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Shinpei Iijima ,  Isamu Asano ,  Yuzuru Ohji ,  Yoshitaka Nakamura

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01G4/008

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L28/55

摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

摘要翻译： 一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素 选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

公开(公告)号：US06710610B1

公开(公告)日：2004-03-23

申请号：US09407838

申请日：1999-09-29

申请人： Naotaka Tanaka ,  Hiroyuki Ohta ,  Ichiro Anjoh ,  Hideo Arima ,  Akio Hasebe ,  Kenichi Yamamoto

发明人： Naotaka Tanaka ,  Hiroyuki Ohta ,  Ichiro Anjoh ,  Hideo Arima ,  Akio Hasebe ,  Kenichi Yamamoto

IPC分类号： G01R3102

CPC分类号： G01R1/0441 ,  H05K3/326

摘要： Electrode pads are formed on a tape circuit to correspond to positions of solder bumps on an IC. A plurality of pins formed on a periphery of the tape circuit provide electrical connection between the tape circuit and a mother socket. An elastomer sheet is provided between a portion of the tape circuit, on which the electrode pads are formed and the IC is mounted, and the mother socket, and a side surface of the sheet, which contacts with the tape circuit, is formed with cut grooves in lattice fashion such that respective centers of the electrode pads substantially coincide with intersections of the grooves. Thus portions defined by the grooves on the sheet are made independent from one another to enable accommodating pushing forces from the solder bumps, so that, even if dispersion in height generates between the solder bumps, the respective portions defined by the grooves are hardly influenced by one another, and so accommodate the pushing forces from the solder bumps to permit the solder bumps and the electrode pads to surely contact with each other.

摘要翻译： 电极焊盘形成在磁带电路上以对应于IC上的焊料凸块的位置。 形成在磁带电路的周边上的多个引脚在磁带电路和母插座之间提供电连接。 弹性体片材设置在带状电路的形成有电极垫的部分和安装有IC的部分之间，并且母带和与带电路接触的片材的侧表面形成有切口 凹槽以格子方式使得电极垫的各个中心基本上与凹槽的交叉重合。 因此，由片上的凹槽限定的部分彼此独立，以便能够容纳来自焊料凸块的推力，使得即使在焊料凸块之间产生高度分散，由凹槽限定的各个部分几乎不受 并且因此容纳来自焊料凸块的推力，以允许焊料凸块和电极焊盘彼此牢固地接触。

公开(公告)号：US6121113A

公开(公告)日：2000-09-19

申请号：US025648

申请日：1998-02-18

申请人： Hirotaka Takatsuka ,  Hiroyuki Ohta

发明人： Hirotaka Takatsuka ,  Hiroyuki Ohta

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： A method for the production of a semiconductor device comprises the steps of forming a stopper layer on a semiconducting substrate, forming a first opening part in the stopper layer thereby enabling the first opening part to establish an element separating area, etching the semiconducting substrate through the first opening part thereby forming a trench in the semiconducting substrate, partially etching the part of the stopper layer approximating closely to the trench thereby dilating the width of the first opening part, forming an oxide film on the stopper layer, in the first opening part, and inside the trench, removing the part of the oxide film rising above the stopper layer, removing the stopper layer, and contracting the lateral parts of the oxide film protruding from the trench.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成阻挡层，在阻挡层中形成第一开口部分，从而使得第一开口部分能够建立元件分离区域，通过该半导体衬底蚀刻半导电衬底 第一开口部分，从而在半导体衬底中形成沟槽，部分地蚀刻接近于沟槽的阻挡层的部分，从而扩大第一开口部分的宽度，在第一开口部分中在阻挡层上形成氧化膜， 并且在沟槽内部，去除在阻挡层上方升起的氧化膜的部分，去除止动层，并使从沟槽突出的氧化膜的侧部收缩。

公开(公告)号：US5525551A

公开(公告)日：1996-06-11

申请号：US255727

申请日：1994-06-07

申请人： Hiroyuki Ohta

发明人： Hiroyuki Ohta

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/205

CPC分类号： H01L21/02164 ,  H01L21/02271 ,  H01L21/02312 ,  H01L21/31608

摘要： The present invention relates to a method for forming a silicon oxide film on a substrate by the thermal chemical vapor deposition method (thermal CVD method) using a gas mixture of ozone (O.sub.3) and tetraethoxyorthosilicate (TEOS). It is an object of the present invention to provide a method for forming an insulating film in a semiconductor device, in which anomalous deposition of the film at a step portion (a portion of difference in level) is prevented and the film contains less moisture and less organic matter and is superior in smoothness. The present invention includes the steps of exposing the depositing surface of the substrate 14 to tetraethoxyorthosilicate in the absence of oxygen and ozone at the elevated temperature and forming an oxide film 15 on the substrate 14 by the thermal CVD method using a gas mixture of ozone (O.sub.3) and tetraethoxyorthosilicate at a deposition temperature. In a second embodiment HMDS is substituted for TEOS in the pretreatment step.

摘要翻译： 本发明涉及使用臭氧（O3）和原硅酸四乙酯（TEOS）的气体混合物的热化学气相沉积法（热CVD法）在基板上形成氧化硅膜的方法。 本发明的目的是提供一种在半导体器件中形成绝缘膜的方法，其中防止了膜在步骤部分处的异常沉积（水平差异的一部分），并且膜含有较少的水分和 有机质少，平滑度优越。 本发明包括以下步骤：在升高的温度下，在不存在氧和臭氧的情况下将基材14的沉积表面暴露于原硅酸四乙酯，并且通过使用臭氧气体混合物的热CVD方法在基板14上形成氧化膜15 O3）和原硅酸四乙酯。 在第二实施方案中，HMDS在预处理步骤中代替TEOS。

公开(公告)号：US4822441A

公开(公告)日：1989-04-18

申请号：US198230

申请日：1988-05-25

申请人： Hiroyuki Ohta ,  Naoki Yoshida ,  Hideo Goto

发明人： Hiroyuki Ohta ,  Naoki Yoshida ,  Hideo Goto

IPC分类号： H01L21/00 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/67126 ,  Y10T74/20912

摘要： The plastic mold decapsuling apparatus comprises an etchant bottle; a heat tank; an etchant reservoir disposed in the heat tank; at least one decapsuling plastic mold holder; a first etchant feeding pump for selectively circulating the etchant from the etchant bottle to the etchant reservoir and discharging waste etchant; and a second etchant feeding pump for feeding the etchant from the reservoir to the plastic mold holder. Since the etchant bottle can be set as it is without transferring the etchant into another vessel, the etchant handling work is safe. Since a required amount of etchant can previously be heated in a reservoir within the heat tank, it is possible to continuously supply a predetermined amount of etchant heated to a constant temperature, thus improving the speed of decapsuling work. Futher, since the etchant is circulated through the decapsuling plastic mold holder, it is possible to firmly decapsule plastic mold devices by use of a relatively mild etchant such as fuming nitric acid.

摘要翻译： 塑料模具拆封装置包括蚀刻剂瓶; 加热箱 设置在所述加热罐中的蚀刻剂储存器; 至少一个开封塑料模架; 用于选择性地将蚀刻剂从蚀刻剂瓶循环到蚀刻剂储存器并排出废蚀刻剂的第一蚀刻剂进料泵; 以及用于将蚀刻剂从储存器供给到塑料模具保持器的第二蚀刻剂进料泵。 由于蚀刻剂瓶可以原样设置而不将蚀刻剂转移到另一个容器中，所以蚀刻剂处理工作是安全的。 由于可以预先在加热箱内的储存器中加热所需量的蚀刻剂，所以可以连续地供给加热到恒定温度的预定量的蚀刻剂，从而提高解封装工作的速度。 更重要的是，由于蚀刻液通过解封装的塑料模具支架循环，因此可以通过使用相对温和的蚀刻剂（例如发烟硝酸）来使塑料模具装置牢固地脱模。

公开(公告)号：US20120329229A1

公开(公告)日：2012-12-27

申请号：US13603577

申请日：2012-09-05

申请人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

发明人： Yosuke Shimamune ,  Masahiro Fukuda ,  Young Suk Kim ,  Akira Katakami ,  Akiyoshi Hatada ,  Naoyoshi Tamura ,  Hiroyuki Ohta

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

公开(公告)号：US08324040B2

公开(公告)日：2012-12-04

申请号：US12785016

申请日：2010-05-21

申请人： Hiroyuki Ohta

发明人： Hiroyuki Ohta

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L29/7843 ,  H01L21/823412 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device including an n-channel MISFET including source/drain regions 38 formed in a semiconductor substrate 10 with a channel region between them, and a gate electrode 44 of a metal silicide formed over the channel region with a gate insulating film 12 interposed therebetween; and an insulating film 46 formed over the gate electrode 44 from side walls of the gate electrode 44 to an upper surface of the gate electrode 44, having a tensile stress from 1.0 to 2.0 GPa and applying the tensile stress to the channel region.

摘要翻译： 一种半导体器件，包括n沟道MISFET，其包括形成在半导体衬底10中的沟道区域之间的源极/漏极区域38和在沟道区域上形成的金属硅化物的栅电极44，栅极绝缘膜12插入其间 ; 以及从栅电极44的侧壁到栅电极44的上表面的栅电极44的上方形成的绝缘膜46，拉伸应力为1.0〜2.0GPa，并对该沟道区施加拉伸应力。

公开(公告)号：US07906848B2

公开(公告)日：2011-03-15

申请号：US12389071

申请日：2009-02-19

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L23/53238 ,  H01L23/3128 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

摘要： In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

摘要翻译： 在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。 在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触 形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

公开(公告)号：US07906798B2

公开(公告)日：2011-03-15

申请号：US11950102

申请日：2007-12-04

申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

IPC分类号： H01L27/092

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。