公开(公告)号：US09224633B2

公开(公告)日：2015-12-29

申请号：US14340186

申请日：2014-07-24

Applicant: Infineon Technologies AG

Inventor： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/02 ,  H01L21/20 ,  C30B25/18 ,  H01L21/324

CPC classification number: H01L21/76254 ,  C30B25/186 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02598 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76251 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.

Abstract translation: 根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

公开(公告)号：US20150162411A1

公开(公告)日：2015-06-11

申请号：US14101378

申请日：2013-12-10

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Markus Zundel ,  Anton Mauder ,  Andreas Meiser ,  Franz Hirler ,  Hans Weber

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/225

CPC classification number: H01L29/407 ,  H01L21/0223 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02258 ,  H01L21/225 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/3081 ,  H01L21/76802 ,  H01L21/76877 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66696 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method for manufacturing a semiconductor structure is provided, which may include: forming a p-doped region adjacent to an n-doped region in a substrate; carrying out an anodic oxidation to form an oxide layer on a surface of the substrate, wherein the oxide layer in a first portion of the surface extending along the n-doped region has a greater thickness than the oxide layer in a second portion of the surface extending along the p-doped region.

Abstract translation: 提供一种制造半导体结构的方法，其可以包括：在衬底中形成与n掺杂区相邻的p掺杂区; 进行阳极氧化以在衬底的表面上形成氧化物层，其中沿着n掺杂区域延伸的表面的第一部分中的氧化物层具有比表面的第二部分中的氧化物层更大的厚度 沿p掺杂区域延伸。

公开(公告)号：US20150130013A1

公开(公告)日：2015-05-14

申请号：US14080098

申请日：2013-11-14

Applicant: Infineon Technologies AG

Inventor： Holger Hüsken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Rösner ,  Holger Schulze

IPC: H01L29/872 ,  H01L29/47 ,  H01L29/66

CPC classification number: H01L29/872 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/868

Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.

Abstract translation: 半导体器件包括在半导体器件的半导体衬底和邻近半导体衬底设置的导电结构之间的至少一个欧姆接触区域。 此外，半导体器件包括半导体器件的半导体衬底和导电结构之间的至少一个肖特基接触区域。 所述至少一个欧姆接触区域布置成与所述至少一个肖特基接触区域相邻。 半导体衬底包括邻近导电结构设置的第一掺杂层。 在至少一个欧姆接触区域的区域中，第一掺杂层的表面区域的平均掺杂浓度与至少一个肖特基接触区域的区域中的第一掺杂层的表面区域的平均掺杂浓度不同 少于10％。

公开(公告)号：US20140370693A1

公开(公告)日：2014-12-18

申请号：US14470996

申请日：2014-08-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz Hirler ,  Hans Peter Felsl ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/302 ,  H01L29/36

CPC classification number: H01L21/02576 ,  H01L21/302 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.

Abstract translation: 一种制造半导体器件的方法包括：通过形成漂移区来形成半导体二极管，在漂移区中或漂移区上形成第一导电类型的第一半导体区域，并通过第一表面的第一表面电耦合第一半导体区域到第一端子 半导体本体，将沟槽蚀刻到半导体本体中，以及在沟槽中形成第二导电类型的沟道区，并且经由半导体本体的第一表面将沟道区电耦合到第一端。 沟道区的第一侧邻接第一半导体区。

公开(公告)号：US20140335676A1

公开(公告)日：2014-11-13

申请号：US14340186

申请日：2014-07-24

Applicant: Infineon Technologies AG

Inventor： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  C30B25/18

CPC classification number: H01L21/76254 ,  C30B25/186 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02598 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76251 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

Abstract: According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.

Abstract translation: 根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

公开(公告)号：US20130330908A1

公开(公告)日：2013-12-12

申请号：US13966915

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Helmut Strack ,  Armin Willmeroth ,  Hans-Joachim Schulze

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/161 ,  H01L29/165 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7831

Abstract: A semiconductor component with vertical structures having a high aspect ratio and method. In one embodiment, a drift zone is arranged between a first and a second component zone. A drift control zone is arranged adjacent to the drift zone in a first direction. A dielectric layer is arranged between the drift zone and the drift control zone wherein the drift zone has a varying doping and/or a varying material composition at least in sections proceeding from the dielectric.

Abstract translation: 具有高纵横比和垂直结构的半导体元件。 在一个实施例中，漂移区布置在第一和第二组分区之间。 漂移控制区在第一方向上布置成与漂移区相邻。 电介质层布置在漂移区和漂移控制区之间，其中漂移区具有至少在从电介质进行的部分中的变化的掺杂和/或变化的材料组成。

公开(公告)号：US20250113512A1

公开(公告)日：2025-04-03

申请号：US18897117

申请日：2024-09-26

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Hans-Jürgen Thees

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A method of producing a power semiconductor device includes: providing a semiconductor body with a vertically protruding fin covered by an insulation material covered by an electrode material, and an insulating material at least partially covering the electrode material; exposing a portion of the electrode material arranged above an upper portion of the fin; removing the exposed portion of the electrode material to expose the upper portion of the fin, thereby forming a respective recess adjacent to both sides of the exposed upper portion of the fin, the recesses being spatially confined by the insulation material, the electrode material and the insulating material; forming an ILD on top of the exposed portions of the device; and forming a first load terminal above the ILD and configured to contact the upper portion of the fin.

公开(公告)号：US12266718B2

公开(公告)日：2025-04-01

申请号：US17668793

申请日：2022-02-10

Applicant: Infineon Technologies AG

Inventor： Hans-Juergen Thees ,  Alim Karmous ,  Anton Mauder

IPC: H01L29/739 ,  H02M1/08 ,  H03K17/567

Abstract: A voltage-controlled switching device includes a drain/drift region of a first conductivity type formed in a semiconductor portion. A channel region and the drain/drift region are in direct contact with each other. A source region of a second conductivity type and the channel region are in direct contact with each other. A gate electrode and the channel region are capacitively coupled and configured such that, in a an on-state of the voltage-controlled switching device, a first enhancement region of charge carriers corresponding to the first conductivity type forms in the channel region and band-to-band tunneling is facilitated between the source region and the first enhancement region.

公开(公告)号：US11735633B2

公开(公告)日：2023-08-22

申请号：US17080950

申请日：2020-10-27

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Rudolf Elpelt ,  Anton Mauder

IPC: H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7813

Abstract: A silicon carbide device includes a silicon carbide body having a hexagonal crystal lattice with a c-plane and with further main planes. The further main planes include a-planes and m-planes. A mean surface plane of the silicon carbide body is tilted to the c-plane by an off-axis angle. The silicon carbide body includes a columnar portion with column sidewalls. At least three of the column sidewalls are oriented along a respective one of the further main planes. A trench gate structure is in contact with the at least three of the column sidewalls.

公开(公告)号：US20230148156A1

公开(公告)日：2023-05-11

申请号：US18095260

申请日：2023-01-10

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Caspar Leendertz ,  Anton Mauder

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/808 ,  H01L29/739 ,  H01L29/40 ,  H01L29/423 ,  H01L21/308 ,  H01L21/31 ,  H01L21/04 ,  H01L21/311 ,  H01L21/426 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/1608 ,  H01L29/66924 ,  H01L29/0615 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/7397 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/66348 ,  H01L29/4236 ,  H01L21/3083 ,  H01L21/31 ,  H01L21/0415 ,  H01L21/311 ,  H01L21/426 ,  H01L21/046 ,  H01L21/02019 ,  H01L21/0334

Abstract: A semiconductor component includes: a SiC semiconductor body; a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, the trench having a conductive connection structure, a structure width at a bottom of the trench, and a dielectric layer covering sidewalls of the trench; a shielding region along the bottom and having a central section which has a lateral first width; and a contact formed between the conductive connection structure and the shielding region. The conductive connection structure is electrically connected to a source electrode. In at least one doping plane extending approximately parallel to the bottom, a dopant concentration in the central section deviates by not more than 10% from a maximum value of the dopant concentration in the shielding region in the doping plane. The first width is less than the structure width and is at least 30% of the structure width.