公开(公告)号：US20190287904A1

公开(公告)日：2019-09-19

申请号：US16349170

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Bernd Waidhas

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.

公开(公告)号：US20190006318A1

公开(公告)日：2019-01-03

申请号：US15637935

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G06F15/76 ,  H01L21/486 ,  H01L23/481 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1011 ,  H01L2225/1017 ,  H01L2225/1058

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US09601468B2

公开(公告)日：2017-03-21

申请号：US15146811

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01F7/04 ,  H01L25/065 ,  H01L23/32 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09368461B2

公开(公告)日：2016-06-14

申请号：US14280110

申请日：2014-05-16

Applicant: INTEL CORPORATION

Inventor： Sven Albers ,  Georg Seidemann ,  Sonja Koller ,  Stephan Stoeckl ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/05 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/141 ,  H01L2224/16238 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0373

Abstract: Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.

Abstract translation: 这里公开了与集成电路（IC）封装一起使用的接触焊盘。 在一些实施例中，本文公开的接触垫可以设置在IC封装的基板上，并且可以包括金属突出部分和金属凹部。 金属突出部和金属凹部中的每一个可以具有焊料接触表面。 金属凹部的焊接接触表面可以与金属突出部的焊接接触表面间隔开。 本文还公开了相关的设备和技术，并且可以要求保护其他实施例。