公开(公告)号：US09601468B2

公开(公告)日：2017-03-21

申请号：US15146811

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01F7/04 ,  H01L25/065 ,  H01L23/32 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09343389B2

公开(公告)日：2016-05-17

申请号：US14827056

申请日：2015-08-14

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L23/32 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US20150357311A1

公开(公告)日：2015-12-10

申请号：US14827056

申请日：2015-08-14

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09778688B2

公开(公告)日：2017-10-03

申请号：US14779300

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jiamiao Tang ,  Junfeng Zhao ,  Michael P. Skinner ,  Yong She ,  Jiun Hann Sir ,  Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC: H01L23/48 ,  G06F1/16 ,  H01L23/31 ,  A41B1/00 ,  A41D1/06 ,  A41D1/08 ,  A41F9/00 ,  A43B3/00 ,  A43B7/14 ,  A44C5/00 ,  A44C15/00 ,  F03G5/06 ,  G06F1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H02J1/14 ,  H05K1/18

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/002 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

公开(公告)号：US20160343686A1

公开(公告)日：2016-11-24

申请号：US14775550

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Shanggar Periaman ,  Michael P. Skinner

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  A44B1/00 ,  G06F1/16 ,  H01L25/00 ,  G02C11/00 ,  A45C1/06 ,  B43K29/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L25/0655 ,  A44B1/00 ,  A45C1/06 ,  B43K29/00 ,  G02C11/10 ,  G06F1/163 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15158 ,  H01L2924/15192 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161

Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于小尺寸或可佩戴装置的集成电路（IC）封装技术和配置。 在一个实施例中，装置可以包括具有第一侧和与第一侧相对设置的第二侧和设置在第一侧和第二侧之间的侧壁的衬底，侧壁限定衬底的周边，以及多个 布置在基板的第一侧和第二侧之间的贯通基板通孔（TSV）以及布置在第一侧上的第一介电层，并且包括电路径特征以将一个或多个管芯的电信号路由在第一 电介质层。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160247785A1

公开(公告)日：2016-08-25

申请号：US15146811

申请日：2016-05-04

Applicant: Intel Corporation

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

公开(公告)号：US09646953B2

公开(公告)日：2017-05-09

申请号：US14775550

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Kooi Chi Ooi ,  Shanggar Periaman ,  Michael P. Skinner

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  A44B1/00 ,  G06F1/16 ,  H01L25/00 ,  H01L23/48 ,  A45C1/06 ,  B43K29/00 ,  G02C11/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  A44B1/00 ,  A45C1/06 ,  B43K29/00 ,  G02C11/10 ,  G06F1/163 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10155 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15158 ,  H01L2924/15192 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/18161

Abstract: Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20160327977A1

公开(公告)日：2016-11-10

申请号：US14779300

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jiamiao Tang ,  Junfeng Zhao ,  Michael P. Skinner ,  Yong She ,  Jiun Hann Sir ,  Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC: G06F1/16 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H05K1/18 ,  G06F1/18 ,  H01L23/00 ,  H02J1/14 ,  F03G5/06 ,  A43B3/00 ,  A43B7/14 ,  A41B1/00 ,  A41D1/06 ,  A44C5/00 ,  A44C15/00 ,  A41F9/00 ,  A41D1/08 ,  H01L25/065

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/002 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装。 在实施例中，集成电路（IC）封装可以包括柔性衬底。 柔性基板可以具有与其连接的多个模具。 IC封装可以包括具有第一刚性的第一封装材料，其设置在柔性基板上以至少部分地封装多个裸片的每个裸片。 IC封装还可包括设置在柔性基板上的具有第二刚性的第二封装材料。 在实施例中，第二刚性和第一刚度彼此不同。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09142475B2

公开(公告)日：2015-09-22

申请号：US13965746

申请日：2013-08-13

Applicant: INTEL CORPORATION

Inventor： Michael P. Skinner ,  Teodora Ossiander ,  Sven Albers ,  Georg Seidemann

IPC: H01L23/32 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01F7/04 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11332 ,  H01L2224/11522 ,  H01L2224/132 ,  H01L2224/13298 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13444 ,  H01L2224/13464 ,  H01L2224/13469 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06531 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有磁性触点的集成电路（IC）封装组件，以及包含这种磁性触点的对应的制造方法和系统。 第一IC基板可以具有与第一电路径特征耦合的第一磁体。 第二IC基板可以具有与第二电路径特征耦合的第二磁体。 磁体可以嵌入在IC基板和/或电路径特征中。 磁体可以产生延伸穿过第一和第二电路由特征之间的间隙的磁场。 可以将导电磁性颗粒施加到IC基板中的一个或两个以形成跨越间隙延伸的磁互连结构。 在一些实施例中，通过将磁体加热到对应的部分退磁温度（PDT）或居里温度，磁接触件可以去磁。 可以描述和/或要求保护其他实施例。