公开(公告)号：US10283407B2

公开(公告)日：2019-05-07

申请号：US15817554

申请日：2017-11-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/45 ,  H01L23/532

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.

公开(公告)号：US20190101829A1

公开(公告)日：2019-04-04

申请号：US15719608

申请日：2017-09-29

Applicant: International Business Machines Corporation

Inventor： Indira P. Seshadri ,  Ekmini Anuja De Silva ,  Chi-Chun Liu ,  Cheng Chi ,  Jing Guo ,  Luciana Meli Thompson

IPC: G03F7/11 ,  G03F7/16

Abstract: Embodiments of the present invention provide systems and methods for trapping amines. This in turn mitigates the undesired scumming and footing effects in a photoresist. The polymer brush is grafted onto a silicon nitride surface. The functional groups and molecular weight of the polymer brush provide protons and impose steric hindrance, respectively, to trap amines diffusing from a silicon nitride surface.

公开(公告)号：US20190080958A1

公开(公告)日：2019-03-14

申请号：US15703097

申请日：2017-09-13

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Kafai Lai ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/02356 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76897

Abstract: A method of forming an interconnect element includes forming a trench in a dielectric material. The trench has a width equal to twice a natural pitch of a block copolymer. The block copolymer includes a first polymer and a second polymer. The method includes filling the trench with the block copolymer.

公开(公告)号：US10157798B1

公开(公告)日：2018-12-18

申请号：US15808467

申请日：2017-11-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Min Gyu Sung ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/66

Abstract: A method for forming a semiconductor device includes forming a semiconductor fin over a surface of a substrate and forming sacrificial spacers on first and second sides of the semiconductor fin. The first side opposes the second side. The method includes recessing the surface to expose second and third surfaces, recessing the second surface to form a first cavity between the sacrificial spacers and the substrate on the first side, and recessing the third surface to form a second cavity between the sacrificial spacers and the substrate on the second side. The method includes forming a first bottom spacer in the first cavity and forming a second bottom spacer in the second cavity. A thickness of the first bottom spacer in a direction between the sacrificial spacers and the substrate is substantially equal to a thickness of the second bottom spacer in the same direction.

公开(公告)号：US10157789B2

公开(公告)日：2018-12-18

申请号：US15239178

申请日：2016-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Shyng-Tsong Chen ,  Cheng Chi ,  Chi-Chun Liu ,  Sylvie M. Mignot ,  Yann A. Mignot ,  Hosadurga K. Shobha ,  Terry A. Spooner ,  Wenhui Wang ,  Yongan Xu

IPC: H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

公开(公告)号：US20180337278A1

公开(公告)日：2018-11-22

申请号：US16046123

申请日：2018-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L29/7827 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7856 ,  H01L29/78642

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US09997403B2

公开(公告)日：2018-06-12

申请号：US15422923

申请日：2017-02-02

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/51 ,  H01L29/45

CPC classification number: H01L21/76837 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/456 ,  H01L29/517

Abstract: Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An interlayer dielectric is formed on top of the intermediate structure. A trench is cut through the interlayer dielectric, through at least one of the trench contacts, down to a shallow trench isolation area. The trench is filled with a filling material. Upper contacts are formed on top of the trench contacts in the interlayer dielectric. A first metal layer pattern is patterned such that a separation is formed by a filling material width of the filling material. First metal layers are formed according to the first metal layer pattern, where tips of the first metal layers are aligned to the filling material that fills the trench, such that the tips of the first metal layers are separated by the filling material width.

公开(公告)号：US20180082850A1

公开(公告)日：2018-03-22

申请号：US15813518

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Cheng Chi ,  Chi-Chun Liu ,  Peng Xu

IPC: H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/31116 ,  H01L29/66795 ,  H01L29/6681

Abstract: A method of forming a semiconductor device and resulting structures having a dummy semiconductor fin removed from within an array of tight pitch semiconductor fins by forming a first spacer including a first material on a substrate; forming a second spacer including a second material on the substrate, the second spacer adjacent to the first spacer; and applying an etch process to the first spacer and the second spacer; wherein the etch process removes the first spacer at a first etch rate; wherein the etch process removes the second spacer at a second etch rate; wherein the first etch rate is different than the second etch rate.

公开(公告)号：US20180012795A1

公开(公告)日：2018-01-11

申请号：US15206789

申请日：2016-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Cheng Chi ,  Lin Hu ,  Kafai Lai ,  Chi-Chun Liu ,  Jed W. Pitera

IPC: H01L21/768 ,  H01L21/02 ,  G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76816 ,  G06F17/5072 ,  H01L21/02118 ,  H01L21/02318 ,  H01L23/5226 ,  H01L23/528

Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.

公开(公告)号：US20170294349A1

公开(公告)日：2017-10-12

申请号：US15623758

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/522 ,  H01L29/06 ,  H01L29/45 ,  H01L27/088 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/45

Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.