公开(公告)号：US20090302406A1

公开(公告)日：2009-12-10

申请号：US12132875

申请日：2008-06-04

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Charles F. Musante ,  Richard J. Rassel

IPC: H01L31/00 ,  H01L21/00

CPC classification number: H01L27/14627 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14636

Abstract: A plurality of image sensor structures and a plurality of methods for fabricating the plurality of image sensor structures provide for inhibited cracking and delamination of a lens capping layer with respect to a planarizing layer within the plurality of image sensor structures. Particular image sensor structures and related methods include at least one dummy lens layer of different dimensions than active lens layer located over a circuitry portion of a substrate within the particular image sensor structures. Additional particular image sensor structures include at least one of an aperture within the planarizing layer and a sloped endwall of the planarizing layer located over a circuitry portion within the particular image sensor structures.

Abstract translation: 多个图像传感器结构和用于制造多个图像传感器结构的多种方法提供了相对于多个图像传感器结构内的平坦化层的透镜封盖层的抑制性破裂和分层。 特定的图像传感器结构和相关方法包括与位于特定图像传感器结构内的衬底的电路部分之上的有源透镜层不同的至少一个虚拟透镜层。 另外特定的图像传感器结构包括平坦化层内的孔径和位于特定图像传感器结构内的电路部分上方的平坦化层的倾斜端壁中的至少一个。

公开(公告)号：US07586139B2

公开(公告)日：2009-09-08

申请号：US11276218

申请日：2006-02-17

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alan Loiseau ,  Richard J. Rassel

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Alan Loiseau ,  Richard J. Rassel

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14689

Abstract: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

Abstract translation: 具有FET像素阵列的成像传感器和形成成像传感器的方法。 每个像素是半导体岛，例如绝缘体上硅（SOI）晶片上的N型硅。 FET形成在一个光电二极管电极中，例如P阱阴极。 滤色器可以附接到岛的相对表面。 保护层（例如，玻璃或石英）或窗口在滤色器处固定到像素阵列。 图像传感器可以从背面照亮，电池布线在电池单元上方。 因此，通过保护层的光学信号被滤色器过滤并被相应的光电传感器选择性地感测。

公开(公告)号：US20090124047A1

公开(公告)日：2009-05-14

申请号：US12353549

申请日：2009-01-14

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L21/70

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US20090045502A1

公开(公告)日：2009-02-19

申请号：US11838917

申请日：2007-08-15

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Edmund J. Sprogis

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L23/3157 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract translation: 形成有可以与衬底隔离或电连接的通孔形成的半导体芯片级封装，以及可以隔离或电连接到衬底的具有通孔的半导体芯片级封装的制造方法。

公开(公告)号：US20080088014A1

公开(公告)日：2008-04-17

申请号：US11528227

申请日：2006-09-26

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Stephen E. Luce ,  Richard J. Rassel ,  Edmund J. Sprogis

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/14618 ,  H01L25/0657 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.

Abstract translation: 用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。 这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。 成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。 互连装置提供例如与手机的空间限制相匹配的CSP。 该布置还利用最小的线长度来降低噪声。 将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

公开(公告)号：US07193289B2

公开(公告)日：2007-03-20

申请号：US10904807

申请日：2004-11-30

Applicant: James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

Inventor： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

IPC: H01L27/14

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

Abstract: An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

Abstract translation: 一种图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

公开(公告)号：US07132339B2

公开(公告)日：2006-11-07

申请号：US11007843

申请日：2004-12-09

Applicant: Andres Bryant ,  Mark D. Jaffe

Inventor： Andres Bryant ,  Mark D. Jaffe

IPC: H01L21/36 ,  H01L21/38

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66772 ,  H01L29/66795

Abstract: An improved transistor structure that decreases source/drain (S/D) resistance without increasing gate-to-S/D capacitance, thereby increasing device operation. S/D structures are formed into recesses formed on a semiconductor wafer through a semiconductor layer and a first layer of a buried insulator having at least two layers. A body is formed from the semiconductor layer situated between the recesses, and the body comprises a top body surface and a bottom body surface that define a body thickness. Top portions of the S/D structures are within and abut the body thickness. An improved method for forming the improved transistor structure is also described and comprises: forming recesses through a semiconductor layer and a first layer of a buried insulator so that a body is situated between the recesses; and forming S/D structures into the recesses so that top portions of the S/D structures are within and abut a body thickness.

公开(公告)号：US06943405B2

公开(公告)日：2005-09-13

申请号：US10604206

申请日：2003-07-01

Applicant: Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

Inventor： Andres Bryant ,  William F. Clark, Jr. ,  David M. Fried ,  Mark D. Jaffe ,  Edward J. Nowak ,  John J. Pekarik ,  Christopher S. Putnam

IPC: H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00 ,  H01L29/76

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

Abstract translation: 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US09543356B2

公开(公告)日：2017-01-10

申请号：US12538194

申请日：2009-08-10

Applicant: Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

Inventor： Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

IPC: H01L27/148 ,  H01L27/146

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

Abstract: CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.

Abstract translation: CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽 像素传感器单元。 在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽 遮光层。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

公开(公告)号：US08796130B2

公开(公告)日：2014-08-05

申请号：US13352851

申请日：2012-01-18

Applicant: Jeffrey P. Gambino ,  Russell T. Herrin ,  Mark D. Jaffe ,  Laura J. Schutz

Inventor： Jeffrey P. Gambino ,  Russell T. Herrin ,  Mark D. Jaffe ,  Laura J. Schutz

IPC: H01L21/3205

CPC classification number: H01L21/823842 ,  H01L21/28052

Abstract: A method patterns a polysilicon gate over two immediately adjacent, opposite polarity transistor devices. The method patterns a mask over the polysilicon gate. The mask has an opening in a location where the opposite polarity transistor devices abut one another. The method then removes some (a portion) of the polysilicon gate through the opening to form at least a partial recess (or potentially a complete opening) in the polysilicon gate. The recess separates the polysilicon gate into a first polysilicon gate and a second polysilicon gate. After forming the recess, the method dopes the first polysilicon gate using a first polarity dopant and dopes the second polysilicon gate using a second polarity dopant having an opposite polarity of the first polarity dopant.

Abstract translation: 一种在两个紧邻的相反极性的晶体管器件上形成多晶硅栅极的方法。 该方法在多晶硅栅极上形成掩模。 掩模在相反极性晶体管器件彼此邻接的位置处具有开口。 然后，该方法通过开口去除多晶硅栅极的一些（一部分），以在多晶硅栅极中形成至少一个部分凹槽（或潜在的完整开口）。 凹槽将多晶硅栅极分离成第一多晶硅栅极和第二多晶硅栅极。 在形成凹槽之后，该方法使用第一极性掺杂剂掺杂第一多晶硅栅极，并使用具有与第一极性掺杂剂相反极性的第二极性掺杂剂掺杂第二多晶硅栅极。