公开(公告)号：US20180349302A1

公开(公告)日：2018-12-06

申请号：US16058793

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F13/16 ,  G11C8/06 ,  G11C7/10 ,  G11C7/22

Abstract: Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

公开(公告)号：US20180129424A1

公开(公告)日：2018-05-10

申请号：US15345919

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Marco Dallabora ,  Paolo Amato ,  Danilo Caraccio ,  Daniele Balluchi

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C13/00

CPC classification number: G06F3/0611 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0649 ,  G06F3/0658 ,  G06F3/068 ,  G06F3/0685 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

公开(公告)号：US09577611B2

公开(公告)日：2017-02-21

申请号：US14448706

申请日：2014-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Balluchi ,  Daniele Vimercati ,  Graziano Mirichigni

IPC: G11C5/14 ,  H03K3/012 ,  G11C7/22 ,  G11C11/4072

CPC classification number: H03K3/012 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4072

Abstract: An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up.

Abstract translation: 集成电路可以具有耦合到缓冲器（24）的时钟输入引脚。 缓冲器可以向诸如存储器的集成电路芯片提供时钟信号（28）。 为了节省电力，缓冲区掉电。 当准备使用时，缓冲区被快速备份。 在一个实施例中，响应于预定数量的时钟信号切换，缓冲器被自动加电。

公开(公告)号：US20150325288A1

公开(公告)日：2015-11-12

申请号：US14270944

申请日：2014-05-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Balluchi ,  Corrado Villa

IPC: G11C13/00 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436 ,  G11C16/3459 ,  G11C2213/79

Abstract: The disclosed technology relates to a memory device configured to perform multiple access operations in response to a single command received through a memory controller and a method of performing the multiple access operations. In one aspect, the memory device includes a memory array comprising a plurality of memory cells and a memory controller. The memory controller is configured to receive a single command which specifies a plurality of memory access operations to be performed on the memory array. The memory controller is further configured to cause the specified plurality of memory access operations to be performed on the memory array.

Abstract translation: 所公开的技术涉及被配置为响应于通过存储器控制器接收的单个命令和执行多址访问操作的方法来执行多次访问操作的存储器件。 在一个方面，存储器件包括包括多个存储器单元和存储器控制器的存储器阵列。 存储器控制器被配置为接收指定要在存储器阵列上执行的多个存储器访问操作的单个命令。 存储器控制器还被配置为使得对存储器阵列执行指定的多个存储器访问操作。

公开(公告)号：US08825979B2

公开(公告)日：2014-09-02

申请号：US14034275

申请日：2013-09-23

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Graziano Mirichigni

IPC: G06F12/00

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0685 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1015 ,  G11C7/1078 ,  G11C7/1084 ,  G11C16/102 ,  G11C16/32 ,  Y02D10/13

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command.

Abstract translation: 非易失性存储器件包括：第一缓冲寄存器，用于接收和存储要存储到经由存储器总线提供的存储器件中的数据。 命令窗口可激活以插入其自身以访问第一缓冲元件和存储器矩阵之间的存储器矩阵。 命令窗口包括第二缓冲器元件，其存储存储在存储器或存储到一组存储器元件中的数据。 在通过接收第一命令开始的数据写入操作的第一阶段期间，第一数据传送装置执行将存储在第二缓冲寄存器中的数据的第一传送到第一缓冲寄存器。 第二数据传送装置接收由存储器总线提供的数据，并且在通过接收第二命令开始的数据写入操作的第二阶段期间，基于接收的数据修改存储在第一缓冲寄存器中的数据。 第一传送装置在数据写入操作的第三阶段期间执行将存储在第一缓冲寄存器中的修改数据的第二传送到第二缓冲寄存器。 响应于与第二命令一起接收由存储器总线接收的信号执行第二传送。

公开(公告)号：US20140019702A1

公开(公告)日：2014-01-16

申请号：US14027088

申请日：2013-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Marco Ferrario ,  Daniele Balluchi

IPC: G06F12/02

CPC classification number: G06F12/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

Abstract: Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.

Abstract translation: 非易失性存储器件的示例性实施例可包括在存储器件的一个或多个输入端接收索引值，并将该索引值存储在存储器件的第一寄存器中。 第一寄存器可以在第一时钟域中实现，并且索引值可以标识在第二时钟域中实现的存储器件的第二寄存器。

公开(公告)号：US20250094343A1

公开(公告)日：2025-03-20

申请号：US18782147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250021262A1

公开(公告)日：2025-01-16

申请号：US18904757

申请日：2024-10-02

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.

公开(公告)号：US20240403177A1

公开(公告)日：2024-12-05

申请号：US18678557

申请日：2024-05-30

Applicant: Micron Technology, Inc.

Inventor： Su Wei Lim ,  Senthil Murugan Thangaraj ,  Marco Sforzin ,  Daniele Balluchi ,  Massimiliano Patriarca ,  Giorgio Servalli ,  Angelo Visconti ,  Antonino Capri’ ,  Garth N. Grubb ,  Amitava Majumdar ,  Miguel Mares

IPC: G06F11/20 ,  G06F11/14

Abstract: Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.

公开(公告)号：US12112057B2

公开(公告)日：2024-10-08

申请号：US17861233

申请日：2022-07-10

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Daniele Balluchi

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods related to a flip-on-precharge disable operation are described herein. In an example, a flip-on-precharge disable operation can include activating a set of memory cells in a memory device to perform a memory access. The memory device can include a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The flip-on-precharge disable operation can further include receiving signaling indicative of a command for a precharge operation on a set of the plurality of sets of memory cells. The signaling can include one or more bits that indicates whether to disable a randomly performed flip operation on the set of memory cells. The flip-on-precharge disable operation can include, in response to the one or more bits indicating to disable the flip operation, performing the precharge operation without randomly performing the flip operation on the set of memory cells.