公开(公告)号：US20090189137A1

公开(公告)日：2009-07-30

申请号：US12362277

申请日：2009-01-29

申请人： Masaharu Kinoshita ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Yoshitaka Sasago ,  Yoshinobu Kimura ,  Akio Shima ,  Mitsuharu Tai ,  Norikatsu Takaura

发明人： Masaharu Kinoshita ,  Motoyasu Terao ,  Hideyuki Matsuoka ,  Yoshitaka Sasago ,  Yoshinobu Kimura ,  Akio Shima ,  Mitsuharu Tai ,  Norikatsu Takaura

IPC分类号： H01L47/00

CPC分类号： H01L21/8221 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1285 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.

摘要翻译： 在相变存储器中，用作选择装置的二极管的电特性非常重要。 然而，由于在使用多晶硅的二极管的膜中存在晶界，所以存在泄漏特性变化很大的问题，难以防止误读。 为了解决这个问题，本发明提供了一种在激光退火中控制非晶硅的温度分布的方法，用于结晶和激活非晶硅，从而控制晶界。 根据本发明，可以降低二极管的电性能的变化，并且可以提高相变存储器的产量。

公开(公告)号：US07385838B2

公开(公告)日：2008-06-10

申请号：US11715918

申请日：2007-03-09

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

公开(公告)号：US20070159871A1

公开(公告)日：2007-07-12

申请号：US11715918

申请日：2007-03-09

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C7/10 ,  G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

公开(公告)号：US07206216B2

公开(公告)日：2007-04-17

申请号：US11057682

申请日：2005-02-15

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

公开(公告)号：US20050185445A1

公开(公告)日：2005-08-25

申请号：US11057682

申请日：2005-02-15

申请人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

发明人： Kenichi Osada ,  Riichiro Takemura ,  Norikatsu Takaura ,  Nozomu Matsuzaki ,  Takayuki Kawahara

IPC分类号： G11C13/00 ,  G06F13/00 ,  G11C11/00 ,  G11C16/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C19/08 ,  H01L27/10 ,  H01L27/105

CPC分类号： G11C13/0004 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3454 ,  G11C2013/0092 ,  G11C2213/82

摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

摘要翻译： 一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。 每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。 流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。 此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。 根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

公开(公告)号：US20070029676A1

公开(公告)日：2007-02-08

申请号：US11489668

申请日：2006-07-20

申请人： Norikatsu Takaura ,  Nozomu Matsuzaki

发明人： Norikatsu Takaura ,  Nozomu Matsuzaki

IPC分类号： H01L23/52

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1675

摘要： A resistor element formed of a peel-preventive film, a recording layer made of chalcogenide, and an upper electrode film is formed on a semiconductor substrate, first and second insulation films are formed so as to cover the resistor element, a via hole for exposing the upper electrode film is formed through the first and second insulation films, and a plug for electrical connection to the upper electrode film is formed in the via hole. To form the via hole, the first insulation film made of silicon nitride is used as an etching stopper to perform dry etching on the second insulation film. Then, dry etching is performed on the first insulation film to expose the upper electrode film from the via hole.

摘要翻译： 在半导体衬底上形成由防腐蚀膜，由硫族化物制成的记录层和上电极膜形成的电阻元件，形成第一和第二绝缘膜以覆盖电阻元件，用于暴露的通孔 上电极膜通过第一和第二绝缘膜形成，并且在通孔中形成用于与上电极膜电连接的插头。 为了形成通孔，将由氮化硅制成的第一绝缘膜用作蚀刻停止件，以在第二绝缘膜上进行干蚀刻。 然后，对第一绝缘膜进行干法蚀刻，以使上电极膜从通孔露出。

公开(公告)号：US07098478B2

公开(公告)日：2006-08-29

申请号：US11168872

申请日：2005-06-29

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

公开(公告)号：US20050156150A1

公开(公告)日：2005-07-21

申请号：US10975522

申请日：2004-10-29

申请人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideyuki Matsuoka ,  Norikatsu Takaura

发明人： Tomio Iwasaki ,  Hiroshi Moriya ,  Hideyuki Matsuoka ,  Norikatsu Takaura

IPC分类号： B41M5/26 ,  G11B7/24 ,  G11B7/241 ,  G11B7/243 ,  G11B7/252 ,  G11B7/254 ,  G11B7/257 ,  H01L27/24 ,  H01L29/02 ,  H01L45/00

CPC分类号： G11B7/2403 ,  G11B7/00454 ,  G11B7/243 ,  G11B7/252 ,  G11B7/257 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

摘要： A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.

摘要翻译： 相变存储器包括：基板; 形成在所述基板的主表面上的绝缘膜; 沉积在绝缘膜上的第一电极; 沉积在第一电极上的相变记录膜; 以及沉积在相变记录膜上的第二电极。 相变记录膜包含Ge，Sb和Te中的至少两个作为其主要构成元素。 第一电极包括Ti，Si和N组的材料，或Ta，Si和N组作为其主要构成材料。

公开(公告)号：US20050035428A1

公开(公告)日：2005-02-17

申请号：US10946000

申请日：2004-09-22

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有效区域nwp1和nw1之间的宽度为L4，则有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06670642B2

公开(公告)日：2003-12-30

申请号：US10051188

申请日：2002-01-22

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： H01L2972

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.