公开(公告)号：US12243865B2

公开(公告)日：2025-03-04

申请号：US18100152

申请日：2023-01-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Johann Alsmeier ,  James Kai ,  Koichi Matsuno

IPC: H10B43/27 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B43/40 ,  H10B41/27

Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.

公开(公告)号：US11996153B2

公开(公告)日：2024-05-28

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Yuki Mizutani ,  Hisakazu Otoi ,  Masaaki Higashitani ,  Hiroyuki Ogawa

IPC: G11C16/08 ,  G11C8/14 ,  G11C16/04 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  G11C8/14 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20240055051A1

公开(公告)日：2024-02-15

申请号：US17888063

申请日：2022-08-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  YenLung Li ,  James Kai

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: Technology is disclosed herein reconfiguring word lines as either data word lines or dummy word lines. In a sub-block mode reconfigurable word lines are used as dummy word lines that provide electrical isolation between data word lines in a block. The block may be divided into an upper tier, a middle tier, and a lower tier, with the reconfigurable word lines within the middle tier. In a full-block mode the reconfigurable group of the word lines are used as data word lines. Because the reconfigurable word lines are used as data word lines in the full-block mode storage capacity is greater in the full-block mode than in the sub-block mode. Moreover, because the sub-blocks are smaller in size but greater in number than the full-blocks, the memory system may be provisioned with fewer blocks and still meet user storage requirements in both the full-block mode and the sub-block mode.

公开(公告)号：US11805649B2

公开(公告)日：2023-10-31

申请号：US17385728

申请日：2021-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Srinivas Pulugurtha ,  Johann Alsmeier ,  Yanli Zhang ,  James Kai

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/762 ,  H01L29/10 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/1037 ,  H10B41/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.

公开(公告)号：US20230282288A1

公开(公告)日：2023-09-07

申请号：US17685613

申请日：2022-03-03

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Deepanshu Dutta ,  Ohwon Kwon ,  James Kai ,  Yuki Mizutani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24

Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line. During some read operations, this allows the memory device to operate with lower power requirements.

公开(公告)号：US11201107B2

公开(公告)日：2021-12-14

申请号：US16829591

申请日：2020-03-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Teruo Okina ,  Akio Nishida ,  James Kai

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L27/11582

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.

公开(公告)号：US11195857B2

公开(公告)日：2021-12-07

申请号：US16816691

申请日：2020-03-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Ching-Huang Lu ,  Murshed Chowdhury ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11519

Abstract: A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.

公开(公告)号：US11127729B2

公开(公告)日：2021-09-21

申请号：US16900098

申请日：2020-06-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Murshed Chowdhury ,  Koichi Matsuno ,  Johann Alsmeier

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.

公开(公告)号：US20200075631A1

公开(公告)日：2020-03-05

申请号：US16558712

申请日：2019-09-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yingda Dong ,  James Kai ,  Christopher J. Petti

IPC: H01L27/11597 ,  H01L27/1159 ,  G11C11/22

Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.

公开(公告)号：US20190280003A1

公开(公告)日：2019-09-12

申请号：US16020817

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kensuke Yamaguchi ,  James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.