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    Structures and Methods for Reducing Dopant Out-diffusion from Implant Regions in Power Devices
    62.
    发明申请
    Structures and Methods for Reducing Dopant Out-diffusion from Implant Regions in Power Devices 有权
    用于降低功率器件中植入区域的掺杂物扩散的结构和方法

    公开(公告)号：US20100065905A1

    公开(公告)日：2010-03-18

    申请号：US12212489

    申请日：2008-09-17

    Applicant: James Pan

    Inventor： James Pan

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/7802 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/0856 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

    Abstract: A semiconductor structure comprises a drift region of a first conductivity type in a semiconductor region. A well region of a second conductivity type is over the drift region. A source region of the first conductivity type is in an upper portion of the well region. A heavy body region of the second conductivity type extends in the well region. The heavy body region has a higher doping concentration than the well region. A first diffusion barrier region at least partially surrounds the heavy body region. A gate electrode is insulated from the semiconductor region by a gate dielectric.

    Abstract translation: 半导体结构包括半导体区域中的第一导电类型的漂移区域。 第二导电类型的阱区域在漂移区域之上。 第一导电类型的源极区位于阱区的上部。 第二导电类型的重体区域在阱区域中延伸。 重体区域的掺杂浓度高于阱区域。 第一扩散阻挡区域至少部分地围绕重体区域。 栅电极通过栅极电介质与半导体区域绝缘​​。

    Technique for Controlling Trench Profile in Semiconductor Structures
    64.
    发明申请
    Technique for Controlling Trench Profile in Semiconductor Structures 有权
    控制半导体结构中沟槽剖面的技术

    公开(公告)号：US20090269896A1

    公开(公告)日：2009-10-29

    申请号：US12109302

    申请日：2008-04-24

    Applicant: Hui Chen ,  Qi Wang ,  Briant Harward ,  James Pan

    Inventor： Hui Chen ,  Qi Wang ,  Briant Harward ,  James Pan

    IPC: H01L21/336

    CPC classification number: H01L21/3065 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

    Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

    Abstract translation: 一种形成半导体结构的方法包括以下步骤。 在半导体区域中使用掩模层形成沟槽，使得沟槽具有第一深度，沿其底部的第一宽度和具有第一斜率的侧壁。 去除掩模层，并且执行斜面蚀刻以使沟槽的侧壁逐渐变细，使得侧壁具有小于第一斜率的第二斜率。

    Multi-operational mode transistor with multiple-channel device structure
    65.
    发明授权
    Multi-operational mode transistor with multiple-channel device structure 失效
    具有多通道器件结构的多工作晶体管

    公开(公告)号：US07544572B2

    公开(公告)日：2009-06-09

    申请号：US11289682

    申请日：2005-11-30

    Applicant: James Pan ,  John Pellerin

    Inventor： James Pan ,  John Pellerin

    IPC: H01L21/336

    CPC classification number: H01L29/7838 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective gate dielectric thicknesses for the different gate dielectrics separating the channels, and different respective silicon channel thicknesses for the different channels.

    Abstract translation: 提供了一种多工作模式晶体管，其中采用具有不同相应操作特性的多个通道。 多个通道具有可独立调节的阈值电压。 阈值电压的独立调整包括在不同通道中提供不同的相应掺杂浓度中的至少一个，用于不同栅极电介质分离沟道的各自的栅介质厚度以及用于不同通道的不同的相应的硅沟道厚度。

    Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorine and hydride gas
    70.
    发明授权
    Forming integrated circuits using selective deposition of undoped silicon film seeded in chlorine and hydride gas 失效
    使用选择性沉积接入氯和氢化物气体的未掺杂硅膜形成集成电路

    公开(公告)号：US07229890B2

    公开(公告)日：2007-06-12

    申请号：US10368069

    申请日：2003-02-18

    Applicant: Randhir P. S. Thakur ,  James Pan

    Inventor： Randhir P. S. Thakur ,  James Pan

    IPC: H01L21/20

    CPC classification number: H01L28/84 ,  C23C16/045 ,  C23C16/24 ,  C23C16/56 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  Y10S438/964

    Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

    Abstract translation: 通过在膜的形成期间流动氯，形成具有增强的选择性的多晶硅膜。 氯作为蚀刻剂，其邻近多晶硅结构的绝缘区域需要形成薄膜。 使用该方法形成用于电容器的底部电极，随后进行退火以产生半透明晶粒（HSG）多晶硅。 多层电容器容器形成在非氧化环境中，使得在层之间不形成氧化物。 所形成的结构被平坦化以形成由掺杂和未掺杂的非晶硅层制成的分离的容器。 将选定的未掺杂层接种在含氯环境中并退火以形成HSG。 形成电介质层和第二电极以完成电池电容器。

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