中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

184 records (took 0.021 seconds)

    Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors
    61.
    发明授权
    Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors 有权
    通过分布式延迟检测和软错误校正保护存储器，数据通路和流水线寄存器以及其他存储元件

    公开(公告)号：US09557936B2

    公开(公告)日：2017-01-31

    申请号：US14587234

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Timothy D. Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran ,  Ramakrishnan Venkatasubramanian

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

    Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

    Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。

    STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS
    63.
    发明公开
    STREAMING ENGINE WITH SHORT CUT START INSTRUCTIONS 审中-公开

    公开(公告)号：US20240296065A1

    公开(公告)日：2024-09-05

    申请号：US18661804

    申请日：2024-05-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy Anderson ,  Joseph Zbiciak

    IPC: G06F9/48 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F15/76

    CPC classification number: G06F9/485 ,  G06F9/30014 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/383 ,  G06F15/76

    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

    Exposing valid byte lanes as vector predicates to CPU
    65.
    发明授权
    Exposing valid byte lanes as vector predicates to CPU 有权

    公开(公告)号：US11941399B2

    公开(公告)日：2024-03-26

    申请号：US17687780

    申请日：2022-03-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Son H. Tran

    IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

    CPC classification number: G06F9/3016 ,  G06F9/3004 ,  G06F9/3013 ,  G06F9/35 ,  G06F9/3851

    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

    BUTTERFLY NETWORK ON LOAD DATA RETURN
    67.
    发明公开
    BUTTERFLY NETWORK ON LOAD DATA RETURN 审中-公开

    公开(公告)号：US20240063827A1

    公开(公告)日：2024-02-22

    申请号：US18498196

    申请日：2023-10-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Duc Quang Bui ,  Timothy David Anderson

    IPC: H03M13/00 ,  G06F9/38 ,  H03M13/27

    CPC classification number: H03M13/6561 ,  G06F9/38 ,  H03M13/2789 ,  H03M13/276

    Abstract: A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.

Patent Agency Ranking