公开(公告)号：US10260150B2

公开(公告)日：2019-04-16

申请号：US15906660

申请日：2018-02-27

Applicant: Tokyo Electron Limited

Inventor： Vinh Luong ,  Akiteru Ko

IPC: C23C16/52 ,  H01L21/32 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  C23C16/455

Abstract: Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.

公开(公告)号：US10170329B2

公开(公告)日：2019-01-01

申请号：US15708264

申请日：2017-09-19

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

IPC: H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments of systems and methods for spacer formation for SAMP techniques are described. In an embodiment a method includes providing a substrate with a spacer having a conformal coating. The method may also include performing a spacer freeze treatment process. Additionally, the method may include performing an etch and clean process on the substrate. Further, the method may include controlling the spacer treatment process and etch and clean process in order to achieve spacer formation objectives.

公开(公告)号：US20180082851A1

公开(公告)日：2018-03-22

申请号：US15708264

申请日：2017-09-19

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

IPC: H01L21/308 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/66795

Abstract: Embodiments of systems and methods for spacer formation for SAMP techniques are described. In an embodiment a method includes providing a substrate with a spacer having a conformal coating. The method may also include performing a spacer freeze treatment process. Additionally, the method may include performing an etch and clean process on the substrate. Further, the method may include controlling the spacer treatment process and etch and clean process in order to achieve spacer formation objectives.

公开(公告)号：US20170256395A1

公开(公告)日：2017-09-07

申请号：US15445042

申请日：2017-02-28

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Akiteru Ko

IPC: H01L21/027 ,  C23C16/34 ,  H01L21/66

CPC classification number: H01L21/0273 ,  C23C16/34 ,  H01L21/31144 ,  H01L22/12

Abstract: Provided is a method for critical dimension (CD) trimming of a structure pattern in a substrate, the method comprising: providing a substrate in a process chamber of a patterning system, the substrate comprising a first structure pattern and an underlying layer, the underlying layer comprising a silicon anti-reflective coating (SiARC) or a silicon oxynitride (SiON) layer, an optical planarization layer, and a target patterning layer; performing an optional CD trimming process of the first structure pattern; performing a series of processes to open the SiARC or SiON layer and performing additional CD trimming if required; and performing a series of processes to open the optical planarization layer, the series of processes generating a final structure pattern, and performing additional CD trimming if required; wherein the planarization layer is one of a group comprising an advance patterning film (APL), an organic dielectric layer (ODL) or a spin-on hardmask (SOH) layer.

公开(公告)号：US09673059B2

公开(公告)日：2017-06-06

申请号：US15009013

申请日：2016-01-28

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Akiteru Ko

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01L21/31144 ,  H01J37/32082 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/32137

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme comprising: providing a substrate having a patterned layer comprising a first mandrel and an underlying layer; performing a first conformal spacer deposition creating a first conformal layer; performing a first spacer reactive ion etch (RIE) process on the first conformal layer, creating a first spacer pattern; performing a first mandrel pull process removing the first mandrel; performing a second conformal spacer deposition creating a second conformal layer; performing a second RIE process creating a second spacer pattern, the first spacer pattern acting as a second mandrel; performing a second mandrel pull process removing the first spacer pattern; and transferring the second spacer pattern into the underlying layer; where the integration targets include patterning uniformity, pulldown of structures, slimming of structures, and gouging of the underlying layer.

公开(公告)号：US20170053793A1

公开(公告)日：2017-02-23

申请号：US15227096

申请日：2016-08-03

Applicant: Tokyo Electron Limited

Inventor： Vinh Luong ,  Akiteru Ko

IPC: H01L21/02 ,  C23C16/52 ,  C23C16/455 ,  H01L21/306 ,  H01L21/311

CPC classification number: C23C16/52 ,  C23C16/45525 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32137 ,  H01L21/32139

Abstract: Provided is a method of forming a spacer sidewall mask, the method comprising: providing a substrate in a process chamber, the substrate having a carbon mandrel pattern and an underlying layer, the underlying layer comprising an amorphous silicon layer above a silicon nitride layer; performing a breakthrough etch process including growth of a conformal native silicon oxide layer, creating an ALD patterned structure; performing a spacer sidewall sculpting process on the ALD patterned structure; performing an amorphous silicon main etch (ME) process on the ALD patterned structure, the ME process causing a spacer oxide open and carbon mandrel removal; and performing an amorphous silicon ME over etch (OE) process on the ALD spacer oxide pattern, the ME OE process transferring the ALD spacer oxide pattern into the amorphous silicon layer, generating a first sculpted pattern comprising a first sculpted sub-structure with a trapezoidal shape.

Abstract translation: 提供一种形成间隔壁侧壁的方法，所述方法包括：在处理室中提供衬底，所述衬底具有碳心轴图案和下层，所述下层包括位于氮化硅层上方的非晶硅层; 执行突破蚀刻工艺，包括保形天然氧化硅层的生长，产生ALD图案化结构; 在ALD图案结构上执行间隔壁侧壁雕刻工艺; 在ALD图案化结构上进行非晶硅主蚀刻（ME）工艺，ME工艺引起间隔氧化物开放和碳芯棒去除; 以及在所述ALD间隔物氧化物图案上对蚀刻（OE）工艺执行无定形硅ME，所述ME OE工艺将所述ALD间隔物氧化物图案转移到所述非晶硅层中，产生包含具有梯形的第一雕刻子结构的第一雕刻图案 形状。

公开(公告)号：US09520270B2

公开(公告)日：2016-12-13

申请号：US14340721

申请日：2014-07-25

Applicant: Tokyo Electron Limited

Inventor： Nihar Mohanty ,  Akiteru Ko ,  Chi-Chun Liu

IPC: H01J37/32 ,  G03F7/40 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3065 ,  B81C1/00

CPC classification number: H01J37/32091 ,  B81C1/00428 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31058

Abstract: Techniques herein include methods for curing a layer of material (such as a resist) on a substrate to enable relatively greater heat reflow resistance. Increasing reflow resistance enables successful directed self-assembly of block copolymers. Techniques include receiving a substrate having a patterned photoresist layer and positioning this substrate in a processing chamber of a capacitively coupled plasma system. The patterned photoresist layer is treated with a flux of electrons by coupling negative polarity direct current power to a top electrode of the plasma processing system during plasma processing. The flux of electrons is accelerated from the top electrode with sufficient energy to pass through a plasma and its sheath, and strike the substrate such that the patterned photoresist layer changes in physical properties, which can include an increased glass-liquid transition temperature.

Abstract translation: 本文的技术包括用于固化衬底上的材料层（例如抗蚀剂）的方法，以使得能够相对更大的耐热回流性。 增加回流电阻使嵌段共聚物成功引导自组装。 技术包括接收具有图案化光致抗蚀剂层的衬底并将该衬底定位在电容耦合等离子体系统的处理室中。 通过在等离子体处理期间将负极性直流电力耦合到等离子体处理系统的顶部电极，用电子束来处理图案化的光致抗蚀剂层。 电子通量从顶部电极以足够的能量被加速以通过等离子体及其鞘，并撞击基板，使得图案化的光致抗蚀剂层的物理性质发生变化，这可能包括玻璃 - 液体转变温度升高。

公开(公告)号：US09257280B2

公开(公告)日：2016-02-09

申请号：US14294278

申请日：2014-06-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Akiteru Ko ,  Angelique D. Raley ,  Kiyohito Ito

IPC: H01L21/308 ,  H01L21/33 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144

Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.

Abstract translation: 一种特别有利于改进自对准图案（SAP）蚀刻工艺的方法。 在这种过程中，当衬底层被蚀刻时，形成在间隔层上的刻面可能在间隔层下面的下层中产生不期望的横向蚀刻。 这会损害所需垂直形式的蚀刻。 底层的蚀刻在至少两个步骤中进行，其中在蚀刻步骤之间形成钝化层或保护层，使得在初始蚀刻期间被部分蚀刻的下层的侧壁被保护。 在形成保护层之后，可以恢复下层的其余部分的蚀刻。

公开(公告)号：US09159575B2

公开(公告)日：2015-10-13

申请号：US14282716

申请日：2014-05-20

Applicant: Tokyo Electron Limited

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01J37/32 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract translation: 描述了在基板上构图栅叠层的方法。 该方法包括在衬底上准备栅极堆叠，其中栅极堆叠包括形成在高k层上的高k层和栅极层。 该方法还包括使用脉冲偏压等离子体蚀刻工艺将形成在栅极层中的图案转移到高k层，以及选择用于脉冲偏压等离子体蚀刻工艺的工艺条件，以实现在衬底中形成的具有深度 小于2纳米（nm）。

公开(公告)号：US20240027900A1

公开(公告)日：2024-01-25

申请号：US17871444

申请日：2022-07-22

Applicant: Tokyo Electron Limited

Inventor： Hamed Hajibabaeinajafabadi ,  Akiteru Ko

IPC: G03F7/004 ,  G03F7/42 ,  G03F7/40 ,  G03F7/32

CPC classification number: G03F7/0043 ,  G03F7/426 ,  G03F7/40 ,  G03F7/325

Abstract: A method of reactive developing a metal oxide resist includes providing a gaseous weak acid to a surface of a patterned metal oxide resist including an exposed portion and an unexposed portion, the gaseous weak acid having an acidity (pKa) greater than −2 and less than about 20, and reactive developing the patterned metal oxide resist using a selective acid-base reaction between the gaseous weak acid and the patterned metal oxide resist to form volatile products. The gaseous weak acid acts as the acid and either the exposed portion or the unexposed portion acts as the base.