公开(公告)号：US20180097109A1

公开(公告)日：2018-04-05

申请号：US15832755

申请日：2017-12-05

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/24 ,  H01L29/16 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US09875928B2

公开(公告)日：2018-01-23

申请号：US14682124

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295

Abstract: A method for fabricating metal interconnect structure is disclosed. The method includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the metal interconnection; and using the spacer as mask to remove part of the first IMD layer for forming an opening in the first IMD layer.

公开(公告)号：US09871138B2

公开(公告)日：2018-01-16

申请号：US15628658

申请日：2017-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/24 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US20170309520A1

公开(公告)日：2017-10-26

申请号：US15158608

申请日：2016-05-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuan-Ying Lai

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first metal gate and a second metal gate are formed on the substrate, in which the first metal gate includes a first work function metal layer, the second metal gate includes a second work function metal layer, the first metal gate and the second metal gate include different size, and the first work function metal layer and the second work function metal layer include different thickness.

公开(公告)号：US20170220728A1

公开(公告)日：2017-08-03

申请号：US15065872

申请日：2016-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Che-Yi Lin ,  En-Chiuan Liou ,  Chia-Hsun Tseng ,  Yi-Ting Chen ,  Chia-Hung Wang ,  Yi-Jing Wang

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F9/7003

Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

公开(公告)号：US09722080B2

公开(公告)日：2017-08-01

申请号：US14960444

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/24 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US09721841B1

公开(公告)日：2017-08-01

申请号：US15140019

申请日：2016-04-27

Applicant: United Microelectronics Corp.

Inventor： Jun-Jie Wang ,  Yu-Lin Wang ,  Ching-Wen Hung ,  En-Chiuan Liou ,  Chih-Sen Huang

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/4916

Abstract: An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.

公开(公告)号：US09583627B2

公开(公告)日：2017-02-28

申请号：US14793721

申请日：2015-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung ,  En-Chiuan Liou

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L29/167 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/18 ,  H01L21/2255 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7834 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a fin-shaped structure thereon and the fin-shaped structure includes a top portion and a bottom portion; forming a gate structure on the fin-shaped structure; forming a cap layer on the top portion of the fin-shaped structure not covered by the gate structure; performing an annealing process to drive germanium from the cap layer to the top portion of the fin-shaped structure; removing the cap layer; and forming an epitaxial layer around the top portion of the fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有鳍状结构的基底，并且所述鳍状结构包括顶部和底部; 在鳍状结构上形成栅极结构; 在未被栅极结构覆盖的鳍状结构的顶部上形成盖层; 执行退火处理以将锗从盖层驱动到鳍状结构的顶部; 去除盖层; 以及围绕所述鳍状结构的顶部部分形成外延层。

公开(公告)号：US09581898B2

公开(公告)日：2017-02-28

申请号：US14685615

申请日：2015-04-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Hsun Tseng ,  Tuan-Yen Yu ,  Po-Tsang Chen ,  Yi-Ting Chen

IPC: G03F1/76 ,  G03F1/80 ,  H01L21/033

CPC classification number: G03F1/76 ,  G03F1/54 ,  G03F1/58 ,  G03F1/70 ,  G03F1/72 ,  G03F1/80 ,  H01L21/0337

Abstract: A manufacturing method of a pattern transfer mask includes the following steps. A basic mask is provided. The basic mask includes a plurality of patterns formed by a patterned absorber layer on a substrate according to a first writing layout. A photolithographic process is then performed by the basic mask to obtain individual depth of focus (iDoF) ranges of each of the patterns and a usable depth of focus (UDoF) range of the patterns. At least one constrain pattern dominating the UDoF range is selected from the patterns in the basic mask. The rest of the patterns except the constrain pattern are non-dominating patterns. A second writing layout is then generated for reducing a thickness of the patterned absorber layer in the constrain pattern or in the non-dominating patterns.

Abstract translation: 图案转印掩模的制造方法包括以下步骤。 提供基本的面具。 基本掩模包括根据第一写入布局在基板上由图案化的吸收层形成的多个图案。 然后通过基本掩模执行光刻处理，以获得每种图案的单独焦点深度（iDoF）范围和图案的可用深度（UDoF）范围。 从基本掩码中的图案中选择至少一个主导UDoF范围的约束图案。 除了约束模式之外的其余模式是非主导模式。 然后生成第二写入布局以减小约束图案中的图案化吸收层的厚度或以非主导图案的方式。

公开(公告)号：US20170053980A1

公开(公告)日：2017-02-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.

Abstract translation: 制造单个扩散断裂的方法包括：提供具有与鳍片交叉的两个栅极结构的翅片和与鳍片交叉的中间伪栅极结构，其中中间伪栅极结构被栅极结构夹持。 之后，形成多个间隔物，并且每个间隔物分别围绕栅极结构和中间虚拟栅极结构。 然后，将中间的虚拟栅极结构和直接位于中间的虚拟栅极结构下面的鳍的一部分去除以形成凹部。 最后，形成凹部中的隔离层以封闭凹部的入口，以便形成嵌入凹槽内的空隙。