公开(公告)号：US20090038143A1

公开(公告)日：2009-02-12

申请号：US12232785

申请日：2008-09-24

申请人： Takeo Kagami ,  Tetsuya Kuwashima ,  Norio Takahashi

发明人： Takeo Kagami ,  Tetsuya Kuwashima ,  Norio Takahashi

IPC分类号： G11B5/127

CPC分类号： G11B5/3906 ,  G11B5/3909 ,  G11B2005/3996 ,  Y10T29/49021 ,  Y10T29/49039 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49046 ,  Y10T29/49048 ,  Y10T29/49052

摘要： A method is provided for manufacturing a magneto-resistive device. The magneto-resistive device is for reducing the deterioration in the characteristics of the device due to annealing. The magneto-resistive device has a magneto-resistive layer formed on one surface side of a base, and an insulating layer formed of two layers and deposited around the magneto-resistive layer. The layer of the insulating layer closest to the base is made of a metal or semiconductor oxide. This layer extends over end faces of a plurality of layers made of different materials from one another, which make up the magneto-resistive device, and is in contact with the end faces of the plurality of layers with the same materials.

摘要翻译： 提供了一种用于制造磁阻装置的方法。 该磁阻装置用于减少由退火引起的器件特性的劣化。 磁阻装置具有形成在基底的一个表面侧上的磁阻层和由两层形成并且沉积在磁阻层周围的绝缘层。 最靠近基底的绝缘层的层由金属或半导体氧化物制成。 该层在由不同材料制成的多个层的端面上延伸，其构成磁阻装置，并且与相同材料的多个层的端面接触。

公开(公告)号：US07388287B2

公开(公告)日：2008-06-17

申请号：US11350745

申请日：2006-02-10

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L23/34

CPC分类号： G01P1/023 ,  G01D11/245 ,  H01L25/16 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2924/00012

摘要： A semiconductor package includes a base plate; a sidewall provided at a periphery of the base plate; a sensor chip retained in a chip accommodation space defined by the sidewall; and a chip installation hole provided in the base plate for installing the sensor chip. The sensor chip is disposed in the chip installation hole provided in the base plate of the case. Accordingly, it is possible to reduce a thickness of the semiconductor package without changing a thickness of the sensor chip. The base plate has a relatively large thickness except for the chip installation hole. Accordingly, even when the semiconductor package is made thinner, rigidity of the base plate is maintained, thereby minimizing a strain in the base plate.

摘要翻译： 半导体封装包括基板; 设置在所述基板的周边的侧壁; 传感器芯片保持在由侧壁限定的芯片容纳空间中; 以及设置在基板上的用于安装传感器芯片的芯片安装孔。 传感器芯片设置在设置在壳体的基板中的芯片安装孔中。 因此，可以在不改变传感器芯片的厚度的情况下减小半导体封装的厚度。 除了芯片安装孔之外，基板具有相对较大的厚度。 因此，即使使半导体封装变薄，也能够维持基板的刚性，从而使基板的应变最小化。

公开(公告)号：US20080012148A1

公开(公告)日：2008-01-17

申请号：US11898449

申请日：2007-09-12

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： B81C1/0023 ,  B81C2203/0154 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An acceleration sensor chip package comprises a frame section, a first semiconductor chip corresponding to an MEMS chip having a plurality of first bumps, a second semiconductor chip having a plurality of second bumps, a substrate on which the first and second semiconductor chips are mounted in parallel with each other and which has a plurality of electrode pads directly connected to the first or second bumps in opposing relationship to the first or second bumps, and external terminals respectively connected to the electrode pads, a closed ring-shaped first sealing section which seals a space defined between the frame section and the substrate so as to surround arrangements of the plurality of first bumps, and a second sealing section which covers the first semiconductor chip, the second semiconductor chip and the first sealing section to seal them.

摘要翻译： 加速度传感器芯片封装包括框架部分，对应于具有多个第一凸块的MEMS芯片的第一半导体芯片，具有多个第二凸块的第二半导体芯片，安装有第一和第二半导体芯片的基板 彼此平行并且具有与第一或第二凸起相对的第一或第二凸块直接连接的多个电极焊盘以及分别连接到电极焊盘的外部端子，密封的环状的第一密封部分 限定在所述框架部分和所述基板之间以围绕所述多个第一凸块的布置的空间;以及覆盖所述第一半导体芯片，所述第二半导体芯片和所述第一密封部分以将其密封的第二密封部。

公开(公告)号：US07230327B2

公开(公告)日：2007-06-12

申请号：US11201380

申请日：2005-08-11

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L23/02 ,  H05K1/14

CPC分类号： G06K19/07728 ,  G06K19/077 ,  H01L23/49855 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC card that has improved endurance and demonstrates increased resistance to cracking of the case and peeling of the substrate when a bending force acts upon the IC card. First protrusions and second protrusions are formed in a recess for fitting a LGA. The second protrusions are connected to the side wall of the recess on the card center side. Because the first protrusions maintaining a constant and correct gap between the bottom portion and LGA, that is, a constant and correct thickness of an adhesive, and the second protrusions are provided, the LGA and case can be reliably bonded together. The boundary portion with the thick portion of the recess on the card center side is a portion where stresses are easily concentrated and cracks can easily occur. However, because the second protrusions provided in the bottom portion of the recess are integrally connected to the side wall, the boundary portion is reinforced and stress concentration is relaxed. As a result, the occurrence of cracking from the boundary portion can be inhibited.

摘要翻译： 具有提高耐久性的IC卡，当弯曲力作用在IC卡上时，表现出增加的外壳开裂性和剥离基板的IC卡。 第一突起和第二突起形成在用于装配LGA的凹部中。 第二突起连接到卡中心侧的凹部的侧壁。 由于第一突起在底部和LGA之间保持恒定且正确的间隙，即粘合剂的厚度恒定且正确，并且设置第二突起，因此可以将LGA和壳体可靠地接合在一起。 卡中心侧的凹部的厚部的边界部分是应力容易集中，容易发生裂纹的部分。 然而，由于设置在凹部的底部的第二突起与侧壁一体地连接，所以边界部分被加强并且应力集中被放宽。 结果，可以抑制从边界部分出现裂纹。

公开(公告)号：US07193329B2

公开(公告)日：2007-03-20

申请号：US10283076

申请日：2002-10-30

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L23/48

CPC分类号： H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10477 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207

摘要： The semiconductor device includes a tabular base metal having an insulating layer provided on a bottom surface thereof, and the insulating layer includes a plurality of wiring patterns, each of which is provided with a connecting pad at one end thereof. A semiconductor chip is adhered at a substantial center of the insulating layer with an adhesive. Electrodes provided on a bottom surface of the semiconductor chip are connected to the other ends of the wiring patterns by wire bonding via wires. The semiconductor chip is molded with a resin. The connecting pads are connected to solder balls via an interposer substrate provided with conductors.

摘要翻译： 半导体器件包括具有设置在其底表面上的绝缘层的片状基底金属，并且绝缘层包括多个布线图案，每个布线图案在其一端设置有连接垫。 半导体芯片用粘合剂粘附在绝缘层的大致中心处。 设置在半导体芯片的底表面上的电极通过导线通过引线接合而连接到布线图案的另一端。 用树脂模制半导体芯片。 连接焊盘通过设置有导体的插入器基板连接到焊球。

公开(公告)号：US20060220260A1

公开(公告)日：2006-10-05

申请号：US11387690

申请日：2006-03-24

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L23/48

CPC分类号： B81C1/0023 ,  B81C2203/0154 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An acceleration sensor chip package comprises a frame section, a first semiconductor chip corresponding to an MEMS chip having a plurality of first bumps, a second semiconductor chip having a plurality of second bumps, a substrate on which the first and second semiconductor chips are mounted in parallel with each other and which has a plurality of electrode pads directly connected to the first or second bumps in opposing relationship to the first or second bumps, and external terminals respectively connected to the electrode pads, a closed ring-shaped first sealing section which seals a space defined between the frame section and the substrate so as to surround arrangements of the plurality of first bumps, and a second sealing section which covers the first semiconductor chip, the second semiconductor chip and the first sealing section to seal them.

摘要翻译： 加速度传感器芯片封装包括框架部分，对应于具有多个第一凸块的MEMS芯片的第一半导体芯片，具有多个第二凸块的第二半导体芯片，安装有第一和第二半导体芯片的基板 彼此平行并且具有与第一或第二凸起相对的第一或第二凸块直接连接的多个电极焊盘以及分别连接到电极焊盘的外部端子，密封的环状的第一密封部分 限定在所述框架部分和所述基板之间以围绕所述多个第一凸块的布置的空间;以及覆盖所述第一半导体芯片，所述第二半导体芯片和所述第一密封部分以将其密封的第二密封部。

公开(公告)号：US20050274541A1

公开(公告)日：2005-12-15

申请号：US10775232

申请日：2004-02-11

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/34 ,  H05K13/04

CPC分类号： H05K3/3452 ,  H05K1/117 ,  H05K13/0465 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2203/0588

摘要： A module circuit board for a semiconductor device by a solder reflow process includes a plurality of pads on which the semiconductor device to be mounted, a plurality of terminals formed on a side edge of the board, a resist film covering an area between said pads and said terminal on the board, and a barrier formed between said pads and said terminals.

摘要翻译： 用于通过焊料回流工艺的半导体器件的模块电路板包括多个焊盘，待安装的半导体器件，其上形成在板的侧边缘上的多个端子，覆盖所述焊盘之间的区域的抗蚀剂膜和 板上的所述端子，以及形成在所述焊盘和所述端子之间的屏障。

公开(公告)号：US20050139985A1

公开(公告)日：2005-06-30

申请号：US10842486

申请日：2004-05-11

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L23/02 ,  H01L23/31 ,  H01L23/495 ,  H01L23/525 ,  H01L25/065 ,  H01L25/10 ,  H01L25/11

CPC分类号： H01L24/06 ,  H01L23/3128 ,  H01L23/49575 ,  H01L23/525 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a multichip package wherein a plurality of semiconductor chip packages (100) in each of which first electrode pads (16a) provided in a main surface of a semiconductor chip, and first bonding pads (20a) and first central bonding pads (18a) formed in an upper area of the main surface are respectively electrically connected by first redistribution wiring layers (24) in a one-to-one correspondence relationship, and second electrode pads (17b), and second bonding pads (22b) and second central bonding pads (18b) formed in an upper area of the main surface are respectively electrically connected by second redistribution wiring layers (26) in a one-to-one correspondence relationship, are stacked on one another.

摘要翻译： 本发明提供一种多芯片封装，其中，在半导体芯片的主表面中设置有第一电极焊盘（16a）的多个半导体芯片封装（100）和第一焊盘（20a）和第一中心焊接 形成在主表面的上部区域的焊盘（18A）分别以一一对应关系由第一再分配布线层（24）电连接，第二电极焊盘（17b）和第二焊盘（ 形成在主表面的上部区域的第二中心接合焊盘（18b）分别通过第二再分配布线层（26）以一对一对应关系彼此电连接。

公开(公告)号：US20050048259A1

公开(公告)日：2005-03-03

申请号：US10911477

申请日：2004-08-05

申请人： Norio Takahashi

发明人： Norio Takahashi

IPC分类号： H01L23/12 ,  H01L23/498 ,  H05K3/00 ,  B32B3/10

CPC分类号： H05K3/0052 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0097 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/2009 ,  H05K2203/1545 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T428/24314 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A substrate frame includes an insulative board (10a) having a pair of ear portions (13) extending along its longitudinal edges; a plurality of wiring substrate regions (11) arranged on the insulative board (10a) between the ear portions (13) at predetermined intervals; and a plurality of slits (15) provided between the wiring substrate regions so as to extend across the ear portions (13) or a plurality grooves (18) around the wiring substrate regions (11).

摘要翻译： 衬底框架包括具有沿其纵向边缘延伸的一对耳部（13）的绝缘板（10a）; 以预定间隔在所述耳部（13）之间布置在所述绝缘板（10a）上的多个布线基板区域（11） 以及设置在所述布线基板区域之间以在所述布线基板区域（11）周围的所述耳部（13）或多个槽（18）延伸的多个狭缝（15）。

公开(公告)号：US20050021427A1

公开(公告)日：2005-01-27

申请号：US10752990

申请日：2004-01-08

申请人： Norio Takahashi ,  Toshiyuki Yamagishi ,  Taiki Sakata

发明人： Norio Takahashi ,  Toshiyuki Yamagishi ,  Taiki Sakata

IPC分类号： G06Q10/06 ,  G06F17/21 ,  G06Q10/00 ,  G06Q50/00 ,  G06F17/60

CPC分类号： G06Q40/02 ,  G06Q40/00 ,  G06Q40/12 ,  G06Q40/125

摘要： When inconsistency occurs between data presented from individual group enterprises, causes of the inconsistency cannot be specified easily in a conventional consolidated settlement processing method. In the embodiments of the invention, an XBRL conversion module converts inputted account data into data resulting from synthesis of standard data and extended data by using a mapping table and transmits the converted data to a data separation module. The data separation module separates the standard data and extended data of the received data and stores these types of data in corresponding storage tables while adding them with information for mutual relevancy. In this manner, when inconsistency occurs during a consolidated settlement process, causes of the inconsistency can be specified easily by acquiring the extended data.

摘要翻译： 当个别集团企业提供的数据出现不一致时，常规合并结算处理方法不能轻易指定不一致的原因。 在本发明的实施例中，XBRL转换模块通过使用映射表将输入的帐户数据转换为由标准数据和扩展数据的合成产生的数据，并将转换的数据发送到数据分离模块。 数据分离模块将接收到的数据的标准数据和扩展数据进行分离，并将这些类型的数据存储在相应的存储表中，同时将它们添加到相互关联的信息中。 以这种方式，当在合并结算过程中发生不一致时，通过获取扩展数据可以容易地指定不一致的原因。