公开(公告)号：US20050036362A1

公开(公告)日：2005-02-17

申请号：US10807454

申请日：2004-03-24

申请人： Yoshihisa Iwata ,  Kentaro Nakajima ,  Masayuki Sagoi ,  Yuui Shimizu

发明人： Yoshihisa Iwata ,  Kentaro Nakajima ,  Masayuki Sagoi ,  Yuui Shimizu

IPC分类号： G11C11/15 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/15

摘要： A semiconductor memory device comprises word lines, bit lines, memory cells, a row decoder, a column decoder, and a write circuit. The word lines are formed along a first direction. The bit lines are formed along a second direction. Memory cells include magneto-resistive elements and are arranged at intersections of the word lines and the bit lines. The row decoder selects at least one of the word lines. The column decoder selects at least one of the bit lines. The write circuit supplies first and second write currents to a selected word line and selected bit line respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line. The write circuit changes the current values of the first and second write currents according to a temperature change.

摘要翻译： 半导体存储器件包括字线，位线，存储单元，行解码器，列解码器和写电路。 字线沿着第一方向形成。 位线沿着第二方向形成。 存储单元包括磁阻元件，并且布置在字线和位线的交点处。 行解码器选择至少一个字线。 列解码器选择至少一个位线。 写入电路分别向所选择的字线和所选位线提供第一和第二写入电流，并将数据写入布置在所选择的字线和所选位线的交点处的选定存储单元。 写入电路根据温度变化改变第一和第二写入电流的电流值。

公开(公告)号：US06842362B2

公开(公告)日：2005-01-11

申请号：US10368609

申请日：2003-02-20

申请人： Katsuyuki Fujita ,  Yoshihisa Iwata

发明人： Katsuyuki Fujita ,  Yoshihisa Iwata

IPC分类号： G11C11/15 ,  G11C8/08 ,  G11C11/16 ,  G11C11/00

CPC分类号： G11C8/08 ,  G11C11/16

摘要： One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, a differential amplifier, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”, an output signal from the NAND circuit becomes “H”, and a write current flows through the write word line. At this moment, a value of the write current is restricted to a value which does not exceed VLIMIT/R1 by the differential amplifier. R1 is a wiring resistance of the write word line.

摘要翻译： 写字线的一端连接到解码器/驱动器单元。 解码器/驱动器单元由P沟道MOS晶体管，N沟道MOS晶体管，差分放大器和NAND电路构成。 当写入，CHRDY和RA1都变为“H”时，来自NAND电路的输出信号变为“H”，并且写入电流流过写入字线。 此时，写入电流的值被差分放大器限制为不超过VLIMIT / R1的值。 R1是写字线的布线电阻。

公开(公告)号：US06724653B1

公开(公告)日：2004-04-20

申请号：US10160058

申请日：2002-06-04

申请人： Yoshihisa Iwata ,  Tomoki Higashi

发明人： Yoshihisa Iwata ,  Tomoki Higashi

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C8/10

摘要： A read block is constituted of a plurality of TMR elements arranged in a lateral direction. One end of each of the TMR elements in the read block is connected in common, and connected to a source line via a read select switch. The other ends of TMR elements are independently connected to read bit lines/write word lines. The read bit lines/write word lines are connected to common data lines via a row select switch. The common data lines are connected to a read circuit.

摘要翻译： 读块由沿横向布置的多个TMR元件构成。 读块中的每个TMR元件的一端被共同连接，并通过读选择开关连接到源极线。 TMR元件的另一端独立地连接到读位线/写字线。 读取位线/写入字线通过行选择开关连接到公共数据线。 公共数据线连接到读取电路。

公开(公告)号：US06717845B2

公开(公告)日：2004-04-06

申请号：US10345253

申请日：2003-01-16

申请人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

发明人： Yoshiaki Saito ,  Katsuya Nishiyama ,  Shigeki Takahashi ,  Minoru Amano ,  Tomomasa Ueda ,  Hiroaki Yoda ,  Yoshiaki Asao ,  Yoshihisa Iwata ,  Tatsuya Kishi

IPC分类号： G11C1115

CPC分类号： G11C11/16

摘要： A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first wiring extending in a first direction on or below the magnetoresistance effect element; a covering layer provided at least both sides of the first wiring, the covering layer being made of magnetic material, and the covering layer having a uniaxial anisotropy in the first direction along which a magnetization of the covering layer occurs easily; and a writing circuit configured to pass a current through the first wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

摘要翻译： 磁存储器包括：具有磁记录层的磁阻效应元件; 在所述磁阻效应元件上或第二方向上延伸的第一布线; 所述覆盖层至少设置在所述第一布线的两侧，所述覆盖层由磁性材料制成，所述覆盖层在容易发生所述覆盖层的磁化的第一方向上具有单轴各向异性; 以及写入电路，被配置为使电流通过第一布线，以便通过由电流产生的磁场将信息记录在磁记录层中。

公开(公告)号：US06172930B2

公开(公告)日：2001-01-09

申请号：US09317167

申请日：1999-05-24

申请人： Yoshihisa Iwata ,  Hideko Oodaira

发明人： Yoshihisa Iwata ,  Hideko Oodaira

IPC分类号： G11C11404

CPC分类号： G11C16/30

摘要： A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

摘要翻译： 公开了一种NAND EEPROM，其能够为每个芯片各种地设置要施加到存储器单元的控制栅极的电压。 半导体芯片包括NAND存储单元阵列和高电压产生电路，用于产生将数据写入存储单元阵列时所需的内部电压VPP的数据写入。 此外，半导体芯片包括设定电压选择电路，用于任意设定由各芯片的高电压产生电路产生的电压VPP的电平，以及多路复用器，向芯片的外部提取设置信号LTF 用于使电压VPP的电平任意设定的信号。

公开(公告)号：US6049494A

公开(公告)日：2000-04-11

申请号：US18315

申请日：1998-02-03

申请人： Koji Sakui ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Koji Sakui ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A semiconductor memory device includes a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable, a select gate connected to a select gate line for connecting a memory cell unit to a bitline, a precharge circuit connected to a first node of the bitline, for supplying a precharge voltage higher than an power supply voltage in programming of data, and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell, wherein channels of the plurality of the memory cells constituting a selected memory cell unit are charged to the precharge voltage in programming of data.

摘要翻译： 半导体存储器件包括：存储单元阵列，其中存储单元单元以矩阵形式布置;每个存储单元单元通过连接多个存储单元构成，每个存储单元可电可重写，连接到选择栅极线用于连接的选择栅极 连接到位线的第一节点的预充电电路，用于在数据编程中提供高于电源电压的预充电电压;以及锁存电路，其经由一位线连接到该位线的第二节点 用于将要编程的数据保存到存储单元中的传输门，其中构成选择的存储单元单元的多个存储单元的通道在数据编程中被充电到预充电电压。

公开(公告)号：US5793696A

公开(公告)日：1998-08-11

申请号：US826820

申请日：1997-04-08

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

公开(公告)号：US5761122A

公开(公告)日：1998-06-02

申请号：US749673

申请日：1996-11-15

申请人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

发明人： Hiroshi Nakamura ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Keniti Imamiya

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115

CPC分类号： G11C16/3477 ,  G11C16/10 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3486 ,  G11C7/00

摘要： A semiconductor memory device includes a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each, of which is arranged at one end of at least one bit line connected to the memory cell array and for latching programming data, a control section for judging whether all of a plurality of latched data included in date latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, a section for detecting potentials of the plurality of the first nodes and for judging whether all data latched by the latch circuits are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and a section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, are the same as the first data or not.

摘要翻译： 半导体存储器件包括半导体衬底，具有存储单元的存储单元阵列，每个存储单元存储矩阵形成在半导体衬底上的数据，多个数据锁存电路，每个数据锁存电路至少布置在一端 连接到存储单元阵列的一位线和用于锁存编程数据的控制部分，用于判断包括在由多个数据锁存电路构成的日期锁存组中的多个锁存数据是否与第一数据相同的控制部分 并且用于根据判断结果控制多个第一节点的电位变化，用于检测多个第一节点的电位的部分和用于判断由锁存电路锁存的所有数据是否与第一数据相同， 用于根据判断结果控制多个第二节点的电位，以及用于检测多个第二节点和fo的电位的部分 r输出由数据锁存电路锁存的所有数据是否与第一数据相同的判断结果。

公开(公告)号：US5734286A

公开(公告)日：1998-03-31

申请号：US245770

申请日：1994-05-18

申请人： Yasuhisa Takeyama ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Hironori Banba ,  Hideko Oodaira

发明人： Yasuhisa Takeyama ,  Junichi Miyamoto ,  Yoshihisa Iwata ,  Hironori Banba ,  Hideko Oodaira

IPC分类号： G11C11/407 ,  H02M3/07 ,  H03K5/15 ,  H03K5/151 ,  H03K5/156 ,  G05F1/46

CPC分类号： H02M3/073 ,  H03K5/15013 ,  H03K5/1515 ,  H03K5/1565

摘要： A semiconductor circuit device includes an oscillator for outputting an oscillating signal, a driving signal generator for generating driving signals having respective phases based on a counting of oscillations of the oscillating signal, and a charge pump circuit driven by the driving signals. A pulse width ratio of the driving signals to one another is constant even when an oscillation period of the oscillating signal output by the oscillator changes, whereby the charge pump operates properly under changing conditions.

摘要翻译： 半导体电路装置包括用于输出振荡信号的振荡器，用于产生基于对振荡信号的振荡的计数的各相的驱动信号的驱动信号发生器和由驱动信号驱动的电荷泵电路。 即使当由振荡器输出的振荡信号的振荡周期改变时，驱动信号的脉冲宽度比也是恒定的，从而在变化的条件下电荷泵正常工作。

公开(公告)号：US5637895A

公开(公告)日：1997-06-10

申请号：US523315

申请日：1995-09-05

申请人： Yoshihisa Iwata ,  Hiroshi Nakamura

发明人： Yoshihisa Iwata ,  Hiroshi Nakamura

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0416 ,  G11C16/0483

摘要： In a non-volatile semiconductor memory device having a memory cell array formed by arranging a plurality of non-volatile reloadable semiconductor memory cells (Mi) and select gate elements on a semiconductor substrate (11) via a gate insulating film (13), each memory cell being formed by interposing an interlayer insulating film (15) between a charge storage layer and a control gate line (16.sub.i), the memory device comprises a plurality of select gate lines (14.sub.i) formed by a wiring layer the same as the charge storage layer of the memory cells, as gate electrodes of the select gate elements; and select gate over-adjacent connect lines (16.sub.9, 16.sub.10) formed by a wiring layer the same as the control gate lines (16.sub.i) of the memory cells and located over the select gate lines (14.sub.9, 14.sub.10) via an insulating film in such a way as to be kept floated without contacting with any other wires and potential nodes.

摘要翻译： 在通过经由栅极绝缘膜（13）在半导体衬底（11）上布置多个非易失性可重载半导体存储单元（Mi）和选择栅极元件而形成的存储单元阵列的非易失性半导体存储器件中， 存储单元通过在电荷存储层和控制栅极线（16i）之间插入层间绝缘膜（15）形成，所述存储器件包括由与所述电荷相同的布线层形成的多个选择栅极线（14i） 存储单元的存储层，作为选择栅极元件的栅电极; 并且选择由与存储单元的控制栅极线（16i）相同的布线层形成的并且位于选择栅极线（149,1410）上方的栅极相邻连接线（169,1610），该绝缘膜经由绝缘膜 一种在不与任何其他电线和潜在节点接触的情况下保持浮动的方式。