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公开(公告)号：US20170366876A1
公开(公告)日：2017-12-21
申请号：US15622607
申请日：2017-06-14
发明人： Vinayak Agrawal , Gaurav Gupta , John Cleary , Ken M. Feen
CPC分类号： H04Q9/00 , G06K9/0002 , H04L25/0272 , H04Q11/00
摘要： Aspects of the embodiments are directed an analog front end circuit (AFE circuit), the AFE circuit including a beamforming circuit configured to receive as an input a plurality of receiver inputs, the receiver inputs coupled to a sensor element. The beamforming circuit can include a plurality of receiver sub-circuits, each sub-circuit including a digital-to-analog converter, a low noise amplifier, and an I/Q mixer circuit element; an adder circuit element at an output of the I/Q mixer circuit element; and a multiplexer coupled to an output of the adder circuit. The AFE can be part of a current sensing device. The current sensing device can include a two-dimensional array of sensor elements.
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公开(公告)号：US20170323879A1
公开(公告)日：2017-11-09
申请号：US15149079
申请日：2016-05-06
发明人： John Twomey , Brian Sweeney , Brian B. Moane
IPC分类号： H01L27/02 , H03K5/08 , H01L29/78 , H03K17/687
CPC分类号： H01L27/0255 , H01L29/7802 , H01L29/7816 , H03K5/08 , H03K17/102 , H03K17/6871 , H03K17/6874
摘要： A bus driver is provided that can withstand over voltages being applied to its output terminal without the protection circuit detracting from the voltage swing that can be provided by the driver. The circuit arrangement also allows transistors having good on state resistance and large tolerance of drain-to-source voltages to be used.
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公开(公告)号：US09806734B1
公开(公告)日：2017-10-31
申请号：US15343361
申请日：2016-11-04
发明人： Arvind Madan , Sandeep Monangi
CPC分类号： H03M1/1245 , H03M1/0624 , H03M1/46
摘要： A successive approximation routine (SAR) analog-to-digital converter integrated circuit can include multiple analog-to-digital converters (ADCs) sharing a reference voltage that can be perturbed by a capacitor array of a digital-to-analog converter (DAC) sampling the reference voltage, which can limit conversion accuracy. Synchronizing every bit trial across the ADCs can improve accuracy but can slow the conversion. Synchronizing a subset of at least one, but fewer than N, bit trials across ADCs can help obtain both speed and robustness. This selected subset can include bit trials corresponding to pro-defined critical events, such as those events for which a stable reference voltage node is particularly desirable.
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公开(公告)号：US09800262B1
公开(公告)日：2017-10-24
申请号：US15258910
申请日：2016-09-07
发明人： Roberto Sergio Matteo Maurino , Sanjay Rajasekhar , Pasquale Delizia , Colin G. Lyden , Gabriel Banarie
摘要： A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.
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公开(公告)号：US09800260B1
公开(公告)日：2017-10-24
申请号：US15343674
申请日：2016-11-04
发明人： Debopam Banerjee
CPC分类号： H03M3/412 , H03M1/124 , H03M3/452 , H03M3/454 , H03M3/458 , H03M3/488 , H04B1/0017 , H04B1/38
摘要： An apparatus comprises a delta-sigma analog-to-digital converter (ADC) and baseband processing circuitry. The delta-sigma ADC includes a plurality of integrator stages connected in series, including a first integrator stage operatively coupled to an input of the delta-sigma ADC; a main quantizer circuit including a main ADC circuit and a main digital-to-analog converter (DAC) circuit, wherein an input to the main ADC circuit is operatively coupled to the plurality of integrator stages; and a first feedback circuit path operatively coupled from an output of the first integrator stage to the input of the delta-sigma ADC, wherein the first feedback circuit path is configured to subtract an output voltage of the first integrator stage from the input of the delta-sigma ADC. The baseband circuitry is configured to activate the first feedback circuit path when detecting that the input voltage increases to cause distortion in the delta-sigma ADC.
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公开(公告)号：US09791480B2
公开(公告)日：2017-10-17
申请号：US13899143
申请日：2013-05-21
发明人： Song Qin
CPC分类号： G01R19/0092 , H02M3/158 , H02M2001/0009
摘要： Apparatus and methods for current sensing in switching regulators include a current sensing circuit to sense current of a power stage of a power converter. The power converter can include first and second transistors. The current sensing circuit comprises a transistor that is a scaled version of one of the transistors of the power converter. A circuit of the current sensing circuit matches a drain-to-source voltage of the transistor of the current sensing circuit to the corresponding transistor of the power converter. A current mirror generates a current that mirrors the current flowing through the transistor of the current sensing circuit. A first resistor converts the mirrored current to a current sensed signal.
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公开(公告)号：US09749125B2
公开(公告)日：2017-08-29
申请号：US14568818
申请日：2014-12-12
摘要： A clock and data recovery (CDR) system may use one or more clock signals in sync with recovered data rate. By accumulating a dithering tuning counter value at a data oversampling rate, a plurality of single bit signals at multiples of the recovered data rate and in sync with the recovered data rate can be accurately generated while utilizing the full range of the accumulator. This plurality of clock signals can be used in various modules in the CDR system and other modules in a transceiver system incorporating the CDR system.
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公开(公告)号：US09748048B2
公开(公告)日：2017-08-29
申请号：US14262188
申请日：2014-04-25
发明人： Padraig L. Fitzgerald , Jo-ey Wong , Raymond C. Goggin , Bernard P. Stenson , Paul Lambkin , Mark Schirmer
CPC分类号： H01H1/0036 , H01H59/0009 , H01H2001/0084 , H01H2059/0018 , H01H2059/0072
摘要： Several features are disclosed that improve the operating performance of MEMS switches such that they exhibit improved in-service life and better control over switching on and off.
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公开(公告)号：US09735741B2
公开(公告)日：2017-08-15
申请号：US14472243
申请日：2014-08-28
CPC分类号： H03F1/3247 , H03F1/3258 , H03F3/19 , H03F3/195 , H03F3/21 , H03F3/245 , H03F2200/451 , H03F2201/3215 , H03F2201/3233
摘要： Aspects of this disclosure relate to a receiver for digital predistortion (DPD). The receiver includes an analog-to-digital converter (ADC) having a sampling rate that is lower than a signal bandwidth of an output of a circuit having an input that is predistorted by DPD. DPD can be updated based on feedback from the receiver. According to certain embodiments, the receiver can be a narrowband receiver configured to observe sub-bands of the signal bandwidth. In some other embodiments, the receiver can include a sub-Nyquist ADC.
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公开(公告)号：US09680386B2
公开(公告)日：2017-06-13
申请号：US14529430
申请日：2014-10-31
发明人： Renjian Xie , Yingyang Ou
CPC分类号： H02M3/33592 , H02M3/3376 , H02M2001/342 , Y02B70/1475 , Y02B70/1491
摘要： This application provides methods and apparatus for controlling aspects of a synchronous rectifier power converter. In an example, an apparatus can include a minimum duty cycle control circuit configured to receive first control signals for one or more switches associated with the synchronous rectifier power converter, to compare a duty cycle of the first control signals to a minimum duty cycle threshold, and to provide second control signals having at least the minimum duty cycle for an active snubber switch of the synchronous rectifier power converter.
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