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61.发明授权公开(公告)号：US10324370B2
公开(公告)日：2019-06-18
申请号：US15256757
申请日：2016-09-06
Applicant: Unimicron Technology Corp.
Inventor： Pu-Ju Lin , Shih-Lian Cheng , Yu-Hua Chen , Cheng-Ta Ko , Jui-Jung Chien , Wei-Tse Ho
IPC: H05K3/00 , G03F1/50 , H05K3/06 , H05K3/24 , G01K7/24 , G01K15/00 , H05K3/10 , H05K3/12 , H05K3/18 , H05K3/42 , G03F7/20
Abstract: A manufacturing method of a circuit substrate is provided. A substrate is provided. A positive photoresist layer is coated on the substrate. Once exposure process is performed on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths.
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公开(公告)号：US10271433B2
公开(公告)日：2019-04-23
申请号：US14855404
申请日：2015-09-16
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen , Shih-Lian Cheng
Abstract: A method of packaging an electrical device including following steps is provided. A circuit board including a substrate and a first conductive pattern is provided. The electrical device having an electrode is disposed on the circuit board. A dielectric layer is formed on the circuit board to cover the electrical device, the electrode and the first conductive pattern, wherein a first caving pattern is formed in the dielectric layer by the first conductive pattern. The dielectric layer is patterned to form a through hole and a second caving pattern connecting with the through hole and exposing the electrode. A conductive material is filled in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern. The substrate is removed.
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公开(公告)号：US20190088401A1
公开(公告)日：2019-03-21
申请号：US15818773
申请日：2017-11-21
Applicant: Unimicron Technology Corp.
Inventor： Chang-Fu Chen , Chun-Hao Chen , Kuan-Hsi Wu , Pi-Te Pan
Abstract: A carrier structure includes a substrate, a first patterned circuit layer and at least one magnetic element. The substrate has a first surface and an opening passing through the substrate. The first patterned circuit layer is disposed on the first surface of the substrate and includes an annular circuit for generating an electromagnetic field. The magnetic element is disposed within the opening of the substrate, wherein the magnetic element couples the annular circuit and acts in response to the magnetic force of the electromagnetic field.
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公开(公告)号：US10211139B2
公开(公告)日：2019-02-19
申请号：US15287729
申请日：2016-10-06
Applicant: Unimicron Technology Corp.
Inventor： Tzyy-Jang Tseng , Yu-Hua Chen , Ra-Min Tain
IPC: H01L23/498 , H01L23/48 , H01L25/10 , H01L21/48 , H01L23/367 , H01L23/31 , C25D5/02 , C25D5/34 , C25D5/48 , C25D7/12 , H05K1/11 , H05K3/46 , H01L23/36 , H05K3/42
Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.
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公开(公告)号：US10123418B1
公开(公告)日：2018-11-06
申请号：US15903049
申请日：2018-02-23
Applicant: Unimicron Technology Corp.
Inventor： Wei-Ti Lin , Chun-Hsien Chien , Fu-Yang Chen
IPC: H05K1/16 , H05K3/10 , H05K1/18 , H05K1/02 , H01F27/06 , H05K1/03 , H05K3/00 , H01F41/04 , H05K1/11
Abstract: A circuit board structure including an insulating layer, first and second dielectric layers, and first and second inductors is provided. The insulating layer includes a first surface, a second surface, and a first conductive through hole. The first dielectric layer is disposed on the first surface. The first inductor is disposed on the first surface and includes a first conductive coil in a solenoid form penetrating the first dielectric layer and a first magnetic flux axis of which the direction is substantially parallel to the first surface. The second dielectric layer is disposed on the second surface. The second inductor is disposed on the second surface and includes a second conductive coil in a solenoid form penetrating the second dielectric layer and a second magnetic flux axis of which the direction is substantially parallel to the second surface. A manufacturing method of a circuit board structure is provided.
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Patent Agency Ranking
公开(公告)号：US10121757B2
公开(公告)日：2018-11-06
申请号：US14953020
申请日：2015-11-27
Applicant: Unimicron Technology Corp.
Inventor： Cheng-Jui Chang
Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.
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公开(公告)号：US20180295723A1
公开(公告)日：2018-10-11
申请号：US16008060
申请日：2018-06-14
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Wen-Fang Liu
CPC classification number: H05K1/111 , H05K1/115 , H05K3/0044 , H05K3/3452 , H05K3/4697 , H05K2201/0376 , H05K2203/0228 , H05K2203/025
Abstract: A manufacturing method of a circuit board structure includes the following steps: providing an inner circuit structure which includes a core layer; performing a build-up process to laminate a first build-up circuit structure on a first patterned circuit layer of the inner circuit structure, wherein the first build-up circuit structure includes an inner dielectric layer, and the inner dielectric layer directly covers an upper surface of the core layer and the first patterned circuit layer; removing a portion of the first build-up circuit structure to form an opening extending from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion of the inner dielectric layer; performing a sandblasting process on a first inner surface of the inner dielectric layer exposed by the opening to at least remove the portion of the inner dielectric layer exposed by the opening.
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公开(公告)号：US10083901B2
公开(公告)日：2018-09-25
申请号：US15853926
申请日：2017-12-25
Applicant: Unimicron Technology Corp.
Inventor： Yu-Hua Chen , Cheng-Ta Ko
IPC: H05K3/46 , H01L23/498 , H01L21/48 , H01L23/00
CPC classification number: H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/562 , H05K3/4682 , H05K3/4688 , H05K2201/096 , H05K2201/10378
Abstract: A method for manufacturing a circuit redistribution structure includes the following steps. A first dielectric is formed on a carrier. Conductive blind vias are formed in the first dielectric. A first circuit redistribution layer is formed on the first dielectric. A second dielectric is formed on the first dielectric. First and second holes are formed on the second dielectric. A trench is formed in the second dielectric to divide the second dielectric into first and second portions. A first portion of the first circuit redistribution layer and the first hole are disposed in the first portion of the second dielectric, and a second portion of the first circuit redistribution layer and the second hole are disposed in the second portion of the second dielectric. Conductive blind vias are formed in the first and second holes, and a second circuit redistribution layer is formed on the second dielectric.
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公开(公告)号：US10039184B2
公开(公告)日：2018-07-31
申请号：US15427061
申请日：2017-02-08
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Wen-Fang Liu
CPC classification number: H05K1/111 , H05K1/115 , H05K3/0044 , H05K3/3452 , H05K3/4697 , H05K2201/0376 , H05K2203/0228 , H05K2203/025
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive via connecting the first and the second patterned circuit layers. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure at least has a cavity, the cavity exposes a portion of the first patterned circuit layer and a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the cavity is a curved surface.
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公开(公告)号：US20180077799A1
公开(公告)日：2018-03-15
申请号：US15822222
申请日：2017-11-27
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Shu-Sheng Chiang , Wei-Ming Cheng
CPC classification number: H05K1/111 , H05K1/0266 , H05K1/0296 , H05K1/0298 , H05K1/09 , H05K1/115 , H05K3/0047 , H05K3/0073 , H05K3/4038 , H05K3/4092 , H05K3/4644 , H05K3/4697 , H05K2201/09036 , H05K2201/094 , H05K2201/09563 , H05K2201/09781 , H05K2203/0376 , H05K2203/163
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive through hole connecting the first and the second patterned circuit layers. The first build-up circuit structure at least has a cavity and an inner dielectric layer. The inner dielectric layer has an opening communicating the cavity and a pad of the first patterned circuit layer is located in the opening. A hole diameter of the opening is smaller than a hole diameter of cavity. An inner surface of the inner dielectric layer exposed by the cavity and a top surface of the pad are coplanar or have a height difference.
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