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    Hierarchical SMP computer system
    61.
    发明申请
    Hierarchical SMP computer system 有权
    分层SMP计算机系统

    公开(公告)号：US20020073164A1

    公开(公告)日：2002-06-13

    申请号：US10073712

    申请日：2002-02-11

    申请人： Sun Microsystems, Inc.

    发明人： Erik E. Hagersten ,  Mark D. Hill

    IPC分类号： G06F015/16 ,  G06F015/167

    CPC分类号： G06F12/0692 ,  G06F12/0284

    摘要： A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to restrict the global transfer of local transactions, a plurality of address partitions are defined: global space, local space, remote read space, and remote read and write space. Process private and local data is accessed using local space. Global data is accessed using global space. In one embodiment, a kernel of the operating system is resident in the local space of each node. Because the memory space where the kernel resides is designated as local space, no other nodes can write to, or corrupt, the node's kernel.

    摘要翻译： 对称多处理系统包括通过分层总线互连的多个节点。 为了允许在节点之间传输数据并限制本地事务的全局传输，定义了多个地址分区：全局空间，本地空间，远程读取空间以及远程读写空间。 使用本地空间访问处理私有数据和本地数据。 使用全局空间访问全局数据。 在一个实施例中，操作系统的内核驻留在每个节点的本地空间中。 因为内核所在的内存空间被指定为本地空间，所以没有其他节点可以写入或损坏该节点的内核。

    Shared memory system for symmetric multiprocessor systems
    62.
    发明授权
    Shared memory system for symmetric multiprocessor systems 失效
    用于对称多处理器系统的共享内存系统

    公开(公告)号：US06226671B1

    公开(公告)日：2001-05-01

    申请号：US09126053

    申请日：1998-07-30

    申请人： Erik E. Hagersten ,  Mark D. Hill

    发明人： Erik E. Hagersten ,  Mark D. Hill

    IPC分类号： G06F1300

    CPC分类号： G06F12/0692 ,  G06F12/0284

    摘要： A shared memory system for symmetric multiprocessing systems including a plurality of physical memory locations in which the locations are either allocated to one node of a plurality of processing nodes, equally distributed among the processing nodes, or unequally distributed among the processing nodes. The memory locations are configured to be accessed by the plurality of processing nodes by mapping all memory locations into a plurality of address partitions within a hierarchy bus. The memory locations are addressed by a plurality of address aliases within the bus while the properties of the address partitions are employed to control transaction access generated in the processing nodes to memory locations allocated locally and globally within the processing nodes.

    摘要翻译： 一种用于对称多处理系统的共享存储器系统，包括多个物理存储器位置，其中位置被分配给多个处理节点中的一个节点，在处理节点之间分布均匀，或者在处理节点之间不等分布。 通过将所有存储器位置映射到层次总线内的多个地址分区中，存储器位置被配置为被多个处理节点访问。 存储器位置由总线内的多个地址别名来寻址，同时使用地址分区的属性来控制处理节点中生成的事务访问到处理节点内本地和全局分配的存储器位置。

    Multi-processor computer system having assignment table processor-dependent help table and address-dependent help table for efficiently managing private and common storage areas
    63.
    发明授权
    Multi-processor computer system having assignment table processor-dependent help table and address-dependent help table for efficiently managing private and common storage areas 失效
    具有分配表处理器相关帮助表和地址相关帮助表的多处理器计算机系统，用于有效管理私有和公共存储区域

    公开(公告)号：US5642495A

    公开(公告)日：1997-06-24

    申请号：US256424

    申请日：1995-12-20

    申请人： Eckhard Michael Ammann ,  Hans Helmut Diel

    发明人： Eckhard Michael Ammann ,  Hans Helmut Diel

    IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F12/06 ,  G06F15/167 ,  G06F15/17 ,  G06F13/00

    CPC分类号： G06F9/544 ,  G06F12/0692 ,  G06F15/17

    摘要： A multi-processor computer system is described that consists of at least two processors equipped with storage means. Each of the processors is assigned at least one private storage area (10) in the storage means. Furthermore, at least one common storage area (16) is provided in the storage means, to which a portion (13) of the private storage area (10) is assigned. Through this storage means arrangement, it is possible, using appropriate commands, to transfer messages between different processors via common storage areas. The management of the private and common storage areas is accomplished using tables, whereby the use of help tables simplifies locating information required for carrying out specific commands.

    摘要翻译： PCT No.PCT / EP93 / 03022 Sec。 371 1995年12月20日第 102（e）日期1995年12月20日PCT提交1993年10月29日PCT公布。 出版物WO94 / 日期1994年5月26日描述了一种多处理器计算机系统，其由至少两个配有存储装置的处理器组成。 每个处理器在存储装置中分配至少一个专用存储区域（10）。 此外，在存储装置中设置至少一个公共存储区域（16），专用存储区域（10）的一部分（13）被分配给该存储装置。 通过这种存储装置的布置，可以使用适当的命令通过公共存储区域在不同处理器之间传送消息。 私有和公共存储区域的管理是使用表格完成的，借此使用帮助表简化了定位执行特定命令所需的信息。

    Address translating apparatus for translating virtual address into real address without depending on processing by CPU
    64.
    发明授权
    Address translating apparatus for translating virtual address into real address without depending on processing by CPU 失效
    地址转换装置，用于将虚拟地址转换为实际地址，而不依赖于CPU的处理

    公开(公告)号：US5349650A

    公开(公告)日：1994-09-20

    申请号：US723011

    申请日：1991-06-28

    申请人： Tatsuya Imakura ,  Mitsuru Sugita

    发明人： Tatsuya Imakura ,  Mitsuru Sugita

    IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F12/08

    CPC分类号： G06F12/0692 ,  G06F15/167

    摘要： An address translating circuit is disclosed for translating a virtual address signal generated from an external CPU into a real address signal applicable to the dual-port random access memory (DPRAM) in the microcomputer. This address translating circuit includes an offset register, an enabling signal generating circuit, and a subtractor provided in the microcomputer. The offset data obtained based upon the difference between an address map handled by the external CPU and an address map handled by the internal CPU is set in the offset register. The enabling signal generating circuit is responsive to the more significant bits of the virtual address signal and the offset data to generate an enabling signal. The subtractor is responsive to the intermediate bits of the virtual address signal and the offset data to generate a translated address signal. Since the address translation is performed by circuit operation without depending on the processing of the external CPU, the burden on the external CPU is reduced

    摘要翻译： 公开了一种地址转换电路，用于将从外部CPU产生的虚拟地址信号转换为适用于微型计算机中的双端口随机存取存储器（DPRAM）的实际地址信号。 该地址转换电路包括偏置寄存器，使能信号发生电路和微机中提供的减法器。 基于由外部CPU处理的地址图和由内部CPU处理的地址映射之间的差异获得的偏移数据被设置在偏移寄存器中。 使能信号发生电路响应于虚拟地址信号和偏移数据的更高有效位以产生使能信号。 减法器响应于虚拟地址信号和偏移数据的中间位，以产生转换的地址信号。 由于通过电路操作执行地址转换，而不依赖于外部CPU的处理，因此减少了外部CPU的负担

    Address transformation circuit arrangement
    66.
    发明授权
    Address transformation circuit arrangement 失效
    地址转换电路布置

    公开(公告)号：US4811212A

    公开(公告)日：1989-03-07

    申请号：US915025

    申请日：1986-10-03

    申请人： Stefan Zuger

    发明人： Stefan Zuger

    IPC分类号： H03M7/02 ,  G06F12/02 ,  G06F12/06 ,  H03M7/30 ,  G06F12/10

    CPC分类号： G06F12/0692 ,  G06F12/0292

    摘要： Two circuit arrangements are described for transforming 2.sup.n global addresses used in a control engineering system having several local units into 2.sup.m local addresses used in one of the units of the system. One of these contains several memories in which subfunctions resulting from a splitting of the transformation function conveying the transformation are stored. The other circuit arrangement contains a single memory which accepts all subfunctions. The transformation function is split into the subfunctions in such a manner that an optimum compromise is achieved between the storage space required for storing the subfunctions and the time required for the transformation.

    摘要翻译： 描述了两个电路布置，用于将具有多个本地单元的控制工程系统中使用的2n个全局地址转换为在系统的一个单元中使用的2m本地地址。 其中一个包含几个存储器，其中存储由转换函数的分裂导致的转换所产生的子功能。 另一电路装置包含接受所有子功能的单个存储器。 转换功能被分成子功能，使得在存储子功能所需的存储空间与转换所需的时间之间达到最佳折中。

    Memory address generator with device address type specifier
    67.
    发明授权
    Memory address generator with device address type specifier 失效
    具有设备地址类型说明符的内存地址生成器

    公开(公告)号：US4799187A

    公开(公告)日：1989-01-17

    申请号：US80722

    申请日：1987-07-30

    申请人： Jeffrey W. Einarson ,  Kin-Ling Cheung

    发明人： Jeffrey W. Einarson ,  Kin-Ling Cheung

    IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/12 ,  G06F13/14 ,  G06F13/16 ,  G06F13/18 ,  G06F13/28 ,  G06F13/36

    CPC分类号： G06F12/0692

    摘要： Address generating apparatus for use in a computer system which includes a bus processor, a memory requiring 24-bit addresses, and a plurality of I/O processors, some of which generates 22-bit addresses and others of which generate 24-bit addresses on a system bus connecting them with the memory. The apparatus provides a 2-bit prefix to the address on the system bus when the address on the bus comes from a 22-bit device. The 22-bit devices are specified by a mask register and the prefixes by a set of prefix registers, one for each of the devices. When bus grant logic in the computer system determines which of the devices is to have control of the system bus, logic in the address generating apparatus determines from the mask register whether the device which is to receive control requires a prefix. If it does, the address generating apparatus outputs the device's prefix to the system bus's two most significant address lines at the same time as the device outputs a 22-bit address to the remaining address lines. The mask register and the prefix register are loadable from the bus processor by means of a bus which is independent of the system bus. On system initialization, the bus processor loads the mask register as required for the I/O devices on the system. During system operation, the bus processor loads prefixes for 22-bit devices as required for the devices to generate addresses for the area of memory from or to which the device is transferring data.

    Chiplet architecture data processing devices and methods
    70.
    发明授权
    Chiplet architecture data processing devices and methods 有权

    公开(公告)号：US12038837B2

    公开(公告)日：2024-07-16

    申请号：US18081939

    申请日：2022-12-15

    申请人： Google LLC

    发明人： Xi Chen ,  Chao Ni ,  Jakob Raymond Jones

    IPC分类号： G06F12/06 ,  G06F9/54 ,  G06F13/40

    CPC分类号： G06F12/0692 ,  G06F9/546 ,  G06F13/404

    摘要： A data processing device incorporates a plurality of chiplets having working elements such as processing and memory elements. At least one of the working elements is operative to generate messages directed to working elements of the same chiplet or another one of the chiplets. Each message includes a global address. An evaluation circuit determines whether the global address of a message is within a range of global addresses assigned to the chiplet. If so, the message passes to a translation circuit which translates the message to a local address for routing to a working element of the chiplet. If not, the message is dispatched to one or more other chiplets.