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公开(公告)号：US12014800B2
公开(公告)日：2024-06-18
申请号：US18108762
申请日：2023-02-13
发明人： Cristinel Zonte , Vijay Raghavan , Iulian C Gradinariu , Gary Peter Moscaluk , Roger Bettman , Vineet Argrawal , Samuel Leshner
CPC分类号： G11C7/22 , G11C5/148 , G11C8/08 , G11C16/26 , G11C16/30 , G11C5/145 , G11C16/0483 , G11C16/32
摘要： Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
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公开(公告)号：US12014793B2
公开(公告)日：2024-06-18
申请号：US17858185
申请日：2022-07-06
发明人： Viktor Markov , Alexander Kotov
CPC分类号： G11C29/50016 , G11C16/14 , G11C16/26 , G11C16/349 , G11C29/50004 , G11C2029/5004 , G11C2029/5006
摘要： A method for screening memory cells includes erasing the memory cells, weakly programming the memory cells to a modified erased state, performing a first read operation on the memory cells after the erasing and the weakly programming, screening any of the memory cells that exhibit a read current during the first read operation below a margin read current threshold M1, baking the memory cells after the first read operation, performing a second read operation on the memory cells after the baking, and screening any of the memory cells that exhibit a read current during the second read operation below the margin read current threshold M1.
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公开(公告)号：US12014784B2
公开(公告)日：2024-06-18
申请号：US17845174
申请日：2022-06-21
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/26 , G11C16/30 , G11C16/3459
摘要： Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.
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公开(公告)号：US12013792B2
公开(公告)日：2024-06-18
申请号：US17842278
申请日：2022-06-16
发明人： Li-Te Chang , Murong Lang , Zhenming Zhou
CPC分类号： G06F12/1027 , G06F12/0692 , G11C16/10 , G11C16/26 , G11C16/349 , G06F2212/68 , G11C16/0483
摘要： A read command is received by a processing device coupled to a memory device. The read command specified a logical address. The processing device translates the logical address into a physical address of a physical block of the memory device, wherein the physical address specifies a wordline and a memory device die. Responsive to determining that the physical block is partially programmed, the processing device identifies a threshold voltage offset associated with the wordline. The processing device computes a modified threshold voltage by applying the threshold voltage offset to a read level associated with the memory device die. The processing device reads the data from the physical block using the modified threshold voltage.
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公开(公告)号：US12009040B2
公开(公告)日：2024-06-11
申请号：US17939756
申请日：2022-09-07
CPC分类号： G11C29/12005 , G11C29/44 , G11C29/46 , G11C16/26 , G11C2207/2254
摘要： A memory device to program a group of memory cells to store multiple bits per memory cell. Each bit per memory cell in the group from a page. After determining a plurality of read voltages of the group of memory cells, the memory device can read the multiple pages of the group using the plurality of read voltages. For each respective page in the multiple pages, the memory device can determine a count of first memory cells in the respective page that have threshold voltages higher than a highest read voltage, among the plurality of read voltages, used to read the respective page. The count of the first memory cells can be compared with a predetermined range of a fraction of memory cells in the respective page to evaluate the plurality of read voltages (e.g., whether any of the read voltages is in a wrong voltage range).
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公开(公告)号：US12009031B2
公开(公告)日：2024-06-11
申请号：US17888294
申请日：2022-08-15
发明人： Ning Wang , Kegang Zhang
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/16 , G11C16/26
摘要： A memory array that includes a plurality of storage cells, a plurality of bit lines, a plurality of memory transistor word lines and a plurality of selection transistor word lines, wherein the storage cells form an array of M rows*N columns; each storage cell includes a selection transistor and a memory transistor connected in series; a source and a gate of each selection transistor are connected, and the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line.
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公开(公告)号：US20240177779A1
公开(公告)日：2024-05-30
申请号：US18319292
申请日：2023-05-17
申请人： SK hynix Inc.
发明人： Hyung Jin CHOI , Chan Sik PARK
摘要： A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells; a sensing circuit connected to the plurality of page buffers respectively, the sensing circuit: performing a sensing operation on the page buffers in units of a plurality of chunks, each chunk including two or more page buffers, among the plurality of page buffers, and outputting a sensing result of each of the plurality of chunks; a verification result output circuit for outputting a final verification result of a target program state, among a plurality of program states to which the memory cells are to be programmed, based on the sensing results of the plurality of chunks; and a control logic for controlling the sensing circuit and the peripheral circuit, based on the final verification result.
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公开(公告)号：US11996143B2
公开(公告)日：2024-05-28
申请号：US17846889
申请日：2022-06-22
申请人： KIOXIA CORPORATION
发明人： Tomoki Nakagawa , Koji Kato , Toshifumi Hashimoto
CPC分类号： G11C11/5642 , G11C5/14 , G11C11/5671 , G11C16/0483 , G11C16/26 , G11C16/30
摘要： A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
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公开(公告)号：US11990191B2
公开(公告)日：2024-05-21
申请号：US17673308
申请日：2022-02-16
申请人： SK hynix Inc.
发明人： Hyung Jin Choi
CPC分类号： G11C16/3459 , G11C7/1039 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/26 , G11C16/3404 , G11C2211/5621 , G11C2211/5622
摘要： A memory device includes a cell group and a control circuit. The cell group includes plural non-volatile memory cells, each capable of storing multi-bit data corresponding to plural program states and an erased state. The control circuit performs at least two partial program operations for programming the multi-bit data in at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation to increase a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plural program states and a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.
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公开(公告)号：US11990190B2
公开(公告)日：2024-05-21
申请号：US18332472
申请日：2023-06-09
申请人： Kioxia Corporation
发明人： Hiroshi Maejima
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/32 , G11C16/3418 , G11C16/3459
摘要： A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
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