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    Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents
    61.
    发明申请
    Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents 失效
    基于栅极感应漏极漏电流的薄硅绝缘体晶圆上的晶体管和逻辑电路

    公开(公告)号：US20050184340A1

    公开(公告)日：2005-08-25

    申请号：US10642416

    申请日：2003-08-15

    申请人： Min-hwa Chi

    发明人： Min-hwa Chi

    IPC分类号： H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

    CPC分类号： H01L29/7841 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78612

    摘要： A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its potential and can thus serve as an output node. The transistor can function as an inverter. The body (either n-well or p-well) is isolated from the n+ or P+ “GIDL switches” by a region of opposite doping type, i.e., p-base and n-base. The basic building blocks of logic circuits, e.g., NAND and NOR gates, are easily implemented with such transistors on thin SOI wafers. These new transistors on thin SOI only need contacts and metal line connections on the VCC and VSS. The connection of fan-outs (between the output and input) can be implemented by capacitor coupling. The transistor structure and operation is useful for high-performance, low-voltage, and low-power VLSI circuits on SOI wafers.

    摘要翻译： 公开了在薄SOI上制造的晶体管结构。 薄SOI上的晶体管具有门控n +和p +结，其用作在结的表面上接通和关断GIDL电流的开关。 GIDL电流将流入浮体并钳位其电位，因此可用作输出节点。 晶体管可以作为逆变器。 物体（n阱或p阱）与n +或P +“GIDL开关”隔离相反掺杂类型的区域，即p基极和n基极。 诸如NAND和NOR门之类的逻辑电路的基本构成块可以用薄SOI晶片上的这种晶体管容易地实现。 薄SOI上的这些新晶体管仅需要V CC和V SS上的触点和金属线路连接。 扇出（输出和输入之间）的连接可以通过电容耦合实现。 晶体管结构和操作对SOI晶圆上的高性能，低电压和低功耗VLSI电路是有用的。

    Method for manufacturing field effect transistor
    65.
    发明授权
    Method for manufacturing field effect transistor 失效
    场效应晶体管的制造方法

    公开(公告)号：US06833589B2

    公开(公告)日：2004-12-21

    申请号：US10075588

    申请日：2002-02-15

    申请人： Hideaki Matsuhashi ,  Yoko Kajita ,  Yoshihiro Koga ,  Toshiyuki Nakamura ,  Jun Kanamori

    发明人： Hideaki Matsuhashi ,  Yoko Kajita ,  Yoshihiro Koga ,  Toshiyuki Nakamura ,  Jun Kanamori

    IPC分类号： H01L29360

    CPC分类号： H01L29/66772 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

    摘要： A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.

    摘要翻译： 用于元件隔离的场氧化膜形成在具有形成在绝缘层上的硅层的SOI衬底上，湿蚀刻活性氮化物膜以将其膜厚度减小到足以允许硅层的边缘 通过使用活性氮化物膜作为掩模，通过垂直或以一定角度的自对准将植入杂质的沟道的离子仅注入硅层的边缘。 通过这种制造方法，实现小栅极长度的场效应晶体管没有寄生晶体管的不利影响，因此不容易发现隆起，并且允许减小nMOS和下一个提供的pMOS之间的距离 相互实现。

    Semiconductor device and method for fabricating the same
    66.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06770517B2

    公开(公告)日：2004-08-03

    申请号：US10028803

    申请日：2001-12-28

    申请人： Hiroaki Nakaoka ,  Hiromasa Fujimoto ,  Atsushi Hori ,  Takashi Uehara ,  Takehiro Hirai

    发明人： Hiroaki Nakaoka ,  Hiromasa Fujimoto ,  Atsushi Hori ,  Takashi Uehara ,  Takehiro Hirai

    IPC分类号： H01L2100

    CPC分类号： H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  Y10S438/91

    摘要： In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.

    摘要翻译： 在形成在绝缘体层上的硅层中，形成与沟道区域和源极/漏极区域相邻的晶格缺陷区域，沟道区域的下部部分作为高浓度沟道区域。 通过在晶格缺陷区域中的复合消除在沟道区域中产生的空穴 - 电子对的空穴，从而抑制由于空穴的积累而产生的双极性运算并增加源极/漏极击穿电压。 寄生晶体管的阈值由高浓度沟道区域增加，以便在OFF状态下减少漏电流。 或者，可以通过提供构成并在沟道和源极区域之间作为pn二极管工作的高浓度扩散层而不是晶格缺陷区域，而将孔移动到源极区域以消失。 因此，可以提供一种SOI晶体管，其不会由于衬底浮置效应而导致的源极/漏极击穿电压降低，并且由于寄生晶体管的激活而导致小的漏电流。

    Method of controlling floating body effects in an asymmetrical SOI device
    67.
    发明授权
    Method of controlling floating body effects in an asymmetrical SOI device 有权
    控制非对称SOI器件浮体效应的方法

    公开(公告)号：US06756637B2

    公开(公告)日：2004-06-29

    申请号：US09899957

    申请日：2001-07-06

    申请人： James W. Adkisson ,  Michael J. Hargrove ,  Lyndon R. Logan ,  Isabel Y. Yang

    发明人： James W. Adkisson ,  Michael J. Hargrove ,  Lyndon R. Logan ,  Isabel Y. Yang

    IPC分类号： H01L2976

    CPC分类号： H01L29/78612 ,  H01L21/26586

    摘要： High performance asymmetric transistors including controllable diode characteristics at the source and/or drain are developed by supplying impurities with high accuracy of location by angled implants in a trench or diffusion from a solid body formed as a sidewall of doped material. High concentration gradient of impurities to support high performance is achieved by providing for reduced heat treatment after the impurity is supplied in order to limit diffusion previously necessary to achieve the desired location of impurity structures. Damascene or quasi-Damascene gate structures are also provided for high dimensional uniformity, increased manufacturing yield and structural integrity of the transistor.

    摘要翻译： 在源极和/或漏极处包括可控二极管特性的高性能不对称晶体管通过在沟槽中的倾斜注入提供高精度的杂质或从形成为掺杂材料的侧壁的固体的扩散而开发。 通过在提供杂质之后提供减少的热处理以便限制先前必需的扩散以实现杂质结构的所需位置来实现高浓度梯度的杂质以支持高性能。 还提供了大马士革或准大马士革门结构，用于高尺寸均匀性，增加的制造产量和晶体管的结构完整性。

    SOI MOS field effect transistor and manufacturing method therefor
    68.
    发明授权
    SOI MOS field effect transistor and manufacturing method therefor 失效
    SOI MOS场效应晶体管及其制造方法

    公开(公告)号：US06750088B2

    公开(公告)日：2004-06-15

    申请号：US10342191

    申请日：2003-01-15

    申请人： Norio Hirashita ,  Takashi Ichimori

    发明人： Norio Hirashita ,  Takashi Ichimori

    IPC分类号： H01L21336

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78618

    摘要： A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

    摘要翻译： 由氧化硅膜构成的器件隔离区域，其被完全隔离到SOI硅层的厚度方向，SOI层的局部变薄的SOI硅层的激活区域形成在 SOI衬底。 提供激活区域中的MOS场效应晶体管的源极扩散层和漏极扩散层，使得根据形成高熔点金属后的SOI硅层的硅化，只形成肖特基结 在激活区域的每个端部处，并且在其每个端部以外的部分处形成PN结。

    Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions
    69.
    发明授权
    Method of fabrication SOI devices with accurately defined monocrystalline source/drain extensions 失效
    制造具有精确定义的单晶源极/漏极延伸的SOI器件的方法

    公开(公告)号：US06743689B1

    公开(公告)日：2004-06-01

    申请号：US10341427

    申请日：2003-01-14

    申请人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

    发明人： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

    IPC分类号： H01L21336

    CPC分类号： H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

    摘要： Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

    摘要翻译： 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。