公开(公告)号：US20170238269A1

公开(公告)日：2017-08-17

申请号：US15493677

申请日：2017-04-21

申请人： DOCKON AG

发明人： Forrest James BROWN ,  Patrick Antoine RADA ,  Alexandre DUPUY

IPC分类号： H04W52/52 ,  H04L7/033 ,  H04L27/14

CPC分类号： H04W52/52 ,  G06G7/24 ,  H03D1/18 ,  H03D3/00 ,  H03D11/04 ,  H03D11/08 ,  H03D2200/006 ,  H04B1/26 ,  H04L7/033 ,  H04L27/14

摘要： A regenerative selective logarithmic detector amplifier (LDA) can have integrated FM demodulation capabilities. It can receive a wired or wireless FM modulated signal and amplify or demodulate it with high sensitivity, high skirt ratio and minimized noise when compared to the prior art. When used in conjunction with other circuits such as a PLL or mixer, it can improve interference rejection and frequency selectivity and be locked on a precise channel in frequency and phase. The LDA produces intermittent oscillations that are self-quenched when reaching a given threshold. It also embeds the circuitry to perform direct FM discrimination. FM demodulation process is completed by a simple analog or digital frequency to voltage converter. This plus the fact that the instantaneous regeneration gain is low-medium permit to detect signals of small amplitudes buried in the noise.

公开(公告)号：US09735948B2

公开(公告)日：2017-08-15

申请号：US14875592

申请日：2015-10-05

申请人： QUALCOMM Incorporated

发明人： Shoichiro Sengoku

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L25/02 ,  H04L7/027

CPC分类号： H04L7/0008 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/0272 ,  H04L25/14

摘要： System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

公开(公告)号：US09722590B1

公开(公告)日：2017-08-01

申请号：US15180146

申请日：2016-06-13

申请人： Hitachi, Ltd.

发明人： Tatsunori Usugi ,  Kouzaburou Kurita ,  Takemasa Komori ,  Junya Nasu

IPC分类号： H04L7/00 ,  H03K5/15 ,  H03L7/08 ,  H04L7/033

CPC分类号： H03K5/15066 ,  H03L7/0807 ,  H03L7/0812 ,  H04L7/033 ,  H04L25/14

摘要： A skew adjustment circuit includes: flip flop circuits for taking in an input signal in response to first clock signals; a clock phase adjustment circuit for adjusting phases of second clock signals, based on the second clock signals generated based on a reference clock signal and an output signal from the flip flop circuits; a phase interval detection circuit for detecting a phase interval between the first clock signals, based on a reference value; and a phase interval adjustment circuit for performing adjustment such that phase intervals become equal to each other between the second clock signals adjusted by the clock phase adjustment circuit, based on a skew adjustment signal from the phase interval detection circuit. The reference value is obtained by calibration, and the second clock signals adjusted by the phase interval adjustment circuit are provided as the first clock signals to the flip flop circuits.

公开(公告)号：US20170214516A1

公开(公告)日：2017-07-27

申请号：US15007967

申请日：2016-01-27

申请人： Daniel Rivaud ,  Kevin Estabrooks ,  Bashar Abdullah

发明人： Daniel Rivaud ,  Kevin Estabrooks ,  Bashar Abdullah

IPC分类号： H04L7/033 ,  H04L29/02 ,  H04L1/00 ,  H04B15/06 ,  H04L12/24

CPC分类号： H04L7/033 ,  H03L7/08 ,  H04B15/06 ,  H04L1/0082 ,  H04L29/02 ,  H04L41/06 ,  H04M2250/10

摘要： A system for managing holdover. The system may include a local oscillator device. The system may include a phase locked loop (PLL) device coupled to the local oscillator device and a reference clock source. The PLL device may obtain a reference clock signal from the reference clock source to produce an extracted clock signal. The system may include a drift monitoring device coupled to the local oscillator device and the PLL device. The drift monitoring device may determine an amount of oscillator drift within the local oscillator device using the extracted clock signal and an oscillator signal from the local oscillator device. The system may include a drift compensation device coupled to the drift monitoring device and the PLL device. The drift compensation device may transmit a drift compensation signal to the PLL device based on the amount of oscillator drift.

公开(公告)号：US09716506B2

公开(公告)日：2017-07-25

申请号：US15261877

申请日：2016-09-10

申请人： PHISON ELECTRONICS CORP.

发明人： Wei-Yung Chen ,  Yu-Chiang Liao

IPC分类号： H03L7/091 ,  G11C7/22 ,  H03L7/087 ,  H03L7/08 ,  H03L7/099 ,  H03L7/107 ,  H03L7/22 ,  G11C7/10

CPC分类号： H03L7/091 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/033

摘要： A phase lock method is provided. The method includes: sampling a data signal according to a plurality of reference clocks and outputting a sampling result; performing a first logic operation according to the sampling result and outputting a first logic result; delaying the first logic result and outputting the delayed first logic result; performing a second logic operation according to the first logic result and the delayed first logic result and outputting a second logic result; outputting a first frequency adjustment signal according to the second logic result; and performing a phase lock according to the first frequency adjustment signal and a frequency of the data signal.

公开(公告)号：US09710011B2

公开(公告)日：2017-07-18

申请号：US14751312

申请日：2015-06-26

申请人： RAMBUS INC.

发明人： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC分类号： G06F1/08 ,  G11C29/02 ,  H04L7/00 ,  G11C29/50 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14 ,  G06F1/12

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

公开(公告)号：US09705669B2

公开(公告)日：2017-07-11

申请号：US14759888

申请日：2014-01-15

申请人： Saturn Licensing LLC

发明人： Yuichi Hirayama ,  Satoshi Okada ,  Yuichi Mizutani

IPC分类号： H04L7/10 ,  H04L7/04 ,  H04B1/16 ,  H04L7/033 ,  H04N21/43 ,  G09G5/00 ,  H04N5/06

CPC分类号： H04L7/10 ,  G09G5/00 ,  G09G5/008 ,  H04B1/16 ,  H04L7/033 ,  H04L7/048 ,  H04N5/06 ,  H04N21/4302

摘要： Provided is a signal processing device including: a valid clock width calculation unit configured to calculate a valid clock width corresponding to a bit rate of a valid section in which a transport stream (TS) packet exists; and a TS clock signal generation unit configured to generate, on a basis of the valid clock width calculated by the valid clock width calculation unit, a TS clock signal by combining clocks with different frequency dividing rates.

公开(公告)号：US09680634B2

公开(公告)日：2017-06-13

申请号：US15218739

申请日：2016-07-25

申请人： CommScope Technologies LLC

发明人： Donald R. McAllister ,  Christopher Goodman Ranson ,  Fred William Phillips

IPC分类号： H04L25/00 ,  H04L7/00 ,  H04J3/06 ,  H04L7/033 ,  H04L1/06 ,  H04W88/08

CPC分类号： H04L7/0087 ,  H04J3/0658 ,  H04L1/0625 ,  H04L1/0631 ,  H04L7/033 ,  H04W88/085

摘要： Method and apparatus for generating a jitter reduced clock signal from signal transmitted over a communication medium includes receiving, with high speed data interface circuitry, a modulated signal that includes a binary encoded data stream. A recovered clock signal is generated from the modulated signal and tracks the long-term drift in the modulated signal. A jitter reduced clock signal is generated by filtering the recovered clock signal with a filtering circuit having a bandwidth sufficient to remove jitter while allowing the jitter reduced clock signal to track the drift in the modulated signal.

公开(公告)号：US09673826B2

公开(公告)日：2017-06-06

申请号：US14840304

申请日：2015-08-31

申请人： Kabushiki Kaisha Toshiba

发明人： Toshitada Saito

IPC分类号： H03L7/06 ,  H03L7/07 ,  H03L7/087 ,  H04L7/033 ,  H03L7/08

CPC分类号： H03L7/07 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H04L7/033

摘要： According to one embodiment, a receiving device includes a first PLL circuit, a second PLL circuit, and a control circuit. The first PLL circuit includes a first VCO and extracts a first clock from a received first packet. The second PLL circuit includes a second VCO and outputs a second clock acquired by multiplying the received clock by N. The control circuit applies a control signal of the second VCO to a first line controlling the first VCO during a first time from start of reception of the first packet.

公开(公告)号：US20170155529A1

公开(公告)日：2017-06-01

申请号：US15376188

申请日：2016-12-12

申请人： Altera Corporation

发明人： Edward Aung ,  Henry Lui ,  Paul Butler ,  John Turner ,  Rakesh Patel ,  Chong Lee

IPC分类号： H04L25/03 ,  H04L7/033 ,  H04L25/02

CPC分类号： H04L25/03273 ,  G11C7/22 ,  G11C7/222 ,  H03L7/07 ,  H03L7/0802 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/187 ,  H03L7/199 ,  H03M9/00 ,  H04L7/0025 ,  H04L7/02 ,  H04L7/033 ,  H04L7/0337 ,  H04L25/0228

摘要： A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.