公开(公告)号：US20240204931A1

公开(公告)日：2024-06-20

申请号：US18558303

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Gang XIONG ,  Yingyang LI ,  Daewon LEE ,  Alexei DAVYDOV

IPC: H04L5/00

CPC classification number: H04L5/001 ,  H04L5/0053

Abstract: Various embodiments herein provide techniques related to a physical downlink control channel (PDCCH) that includes a single downlink control information (DCI). The single DCI may be related to a first set of one or more physical shared channels on a first component carrier (CC) and a second set of two or more physical shared channels on a second component carrier (CC). Other embodiments may be described and/or claimed.

公开(公告)号：US20240203978A1

公开(公告)日：2024-06-20

申请号：US18085116

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Nachiket Venkappayya DESAI ,  Harish KRISHNAMURTHY ,  Han Wui THEN ,  William J. LAMBERT ,  Jingshu YU

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L27/0266 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

Abstract: Layer transfer for Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a GaN device on or above a substrate, the GaN device including a source, a gate and a drain. A silicon-based clamp structure is above substrate, the silicon-based clamp structure over the GaN device in a region that overlaps the source and the gate of the GaN device.

公开(公告)号：US20240203869A1

公开(公告)日：2024-06-20

申请号：US18067031

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Nikhil Jasvant Mehta ,  Charles Henry Wallace

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76892 ,  H01L23/53228 ,  H01L23/53257

Abstract: Methods for fabricating an integrated circuit (IC) device with one or more hybrid metal lines are provided. An example IC device includes a substrate; and a metal line extending, along an axis, over the substrate. The metal line has a first end and a second end along the axis. A portion of the metal line at the first end includes a first electrically conductive material. Another portion of the metal line includes a second electrically conductive material, where the second electrically conductive material is different from the first electrically conductive material. In some instances, the first electrically conductive material is a low-resistive, electrically conductive material, and the second electrically conductive material is a direct etch-compatible, electrically conductive material.

公开(公告)号：US20240203868A1

公开(公告)日：2024-06-20

申请号：US18066301

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Manish Chandhok ,  David Nathan Shykind ,  Richard E. Schenker ,  Florian Gstrein ,  Eungnak Han ,  Nafees Aminul Kabir ,  Sean Michael Pursel ,  Nityan Labros Nair ,  Robert Seidel

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76879

Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.

公开(公告)号：US20240203806A1

公开(公告)日：2024-06-20

申请号：US18085291

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Bai Nie ,  Leonel R. Arana ,  Dingying XU ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Jeremy D. Ecton ,  Haobo Chen ,  Bin Mu

IPC: H01L23/15 ,  C03C17/00 ,  C03C17/06 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  C03C17/004 ,  C03C17/06 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  C03C2217/253 ,  C03C2218/365

Abstract: An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

公开(公告)号：US20240202124A1

公开(公告)日：2024-06-20

申请号：US18067779

申请日：2022-12-19

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Randy Osborne ,  Nadav Bonen

IPC: G06F12/0831 ,  G06F12/0864

CPC classification number: G06F12/0831 ,  G06F12/0864

Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to computing systems implementing a very large cache for one or more processing engines in a shared memory system. According to various embodiments, a snoop filter tracks a hash value of the cached addresses instead of tracking the addresses themselves. Tracking hash values introduces inaccuracy and an inability to easily clean or refresh the snoop filter. A refresh algorithm maintains cache coherency without significant performance degradation. The cache refresh algorithm keeps the accuracy of the snoop filter, hence reducing the latency and power effects of false snoops. Further, the use of hash values reduces the hardware cost over traditional snoop filters.

公开(公告)号：US20240202120A1

公开(公告)日：2024-06-20

申请号：US18083389

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Julius Mandelblat

IPC: G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/1016

Abstract: Techniques and mechanisms for selectively configuring an integrated circuit (IC) chip to provide tag array functionality and/or cache array functionality. In an embodiment, an IC chip comprises a first array of memory cells, a second array of memory cells, and a cache controller. Based on whether the IC chip is coupled to another IC chip, selector circuitry of the IC chip configures one of multiple possible modes of the cache controller. A first mode of the multiple modes is to provide tag array functionality with the first array, and cache array functionality with the second memory cell array. A second mode of the multiple modes is to provide tag array functionality with the second memory cell array, and cache array functionality with a remote array of memory cells. In another embodiment, the cache controller is reconfigured to another mode based on a change to a power consumption characteristic.

公开(公告)号：US20240202002A1

公开(公告)日：2024-06-20

申请号：US18067577

申请日：2022-12-16

Applicant: INTEL CORPORATION

Inventor： Hideki Ido

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30145

Abstract: Techniques for implementing a branch instruction having a misprediction handling hint to prevent instructions on a mispredicted path from getting cancelled are described. In certain examples, a hardware processor core includes a retirement circuit; a branch predictor circuit to predict a predicted path for a branch, and cause a speculative processing of the predicted path; a decode circuit to decode a single instruction into a decoded instruction, the single instruction having a field to indicate the retirement circuit is to allow retirement of the predicted path for the branch that is a misprediction; and an execution circuit to execute the decoded instruction to cause: the retirement circuit to allow the retirement of the predicted path that is the misprediction for the branch when the field is set to a first value, and the retirement circuit to disallow the retirement of the predicted path that is the misprediction for the branch when the field is otherwise.

公开(公告)号：US20240201445A1

公开(公告)日：2024-06-20

申请号：US18553448

申请日：2022-06-28

Applicant: INTEL CORPORATION

Inventor： Richard Laming ,  Nicholas D. Psaila

IPC: G02B6/36 ,  G02B6/38 ,  G02B6/42

CPC classification number: G02B6/3636 ,  G02B6/3676 ,  G02B6/368 ,  G02B6/3688 ,  G02B6/3837 ,  G02B6/423

Abstract: An apparatus for positioning one or more optical fibers relative to the apparatus, comprises a body comprising a monolithic block of material, one or more fiber alignment structures formed in the material of the monolithic block, each fiber alignment structure comprising a groove configured to accommodate a corresponding optical fiber, and one or more apparatus alignment features formed in the material of the monolithic block, wherein the one or more apparatus alignment features are additional to the one or more fiber alignment structures and wherein the one or more apparatus alignment features have a known spatial relationship relative to the one or more fiber alignment structures. The one or more apparatus alignment features may enable passive alignment of the apparatus relative to a member which is separate from the apparatus such as an optical component and/or a photonic chip. When one or more optical fibers are located and/or secured in one or more corresponding fiber alignment structures of the apparatus, the one or more apparatus alignment features may also enable passive alignment of the one or more optical fibers relative to the member.

公开(公告)号：US12015951B2

公开(公告)日：2024-06-18

申请号：US17482025

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Necati Canpolat ,  Dibakar Das ,  Ganesh Venkatesan ,  Chittabrata Ghosh ,  Dave A. Cavalcanti ,  Cheng Chen ,  Juan Fang ,  Laurent Cariou ,  Carlos Cordeiro

IPC: H04W28/24 ,  H04W28/02

CPC classification number: H04W28/24 ,  H04W28/0268

Abstract: A Quality-of-Service (QoS) Management AP is configured to support QoS Management features and to perform a QoS Management Protocol. The AP decodes an Enhanced Add Traffic Stream (E-ADDTS) Request QoS Action Frame (E-ADDTS Req) received from a station (STA) to initiate QoS setup for a traffic stream. The STA may be a QoS Management STA configured to support the QoS Management features and perform the QoS Management protocol. The AP may encode, for transmission to the STA in response to the E-ADDTS Req, an E-ADDTS Response QoS Action Frame (E-ADDTS Resp) which includes a status code to indicate whether the QoS setup has been accepted. When the QoS setup is accepted, the E-ADDTS Resp includes a QoS setup ID within a QoS setup ID field in the E-ADDTS Resp that uniquely identifies the QoS setup for the traffic stream.