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    Bleaching and detergent compositions comprising manganese complex prepared from tetra-aza macrocyclic ligands through a convenient synthesis
    72.
    发明申请
    Bleaching and detergent compositions comprising manganese complex prepared from tetra-aza macrocyclic ligands through a convenient synthesis 有权
    漂白和洗涤剂组合物包含通过方便的合成由四 - 氮杂大环配体制备的锰络合物

    公开(公告)号：US20070072786A1

    公开(公告)日：2007-03-29

    申请号：US11593167

    申请日：2006-11-03

    Applicant: Han Park ,  Sang Lee ,  In Cho ,  Won Kim ,  In Baik

    Inventor： Han Park ,  Sang Lee ,  In Cho ,  Won Kim ,  In Baik

    IPC: C11D3/42

    CPC classification number: C11D3/3935 ,  C11D3/3932

    Abstract: The present invention provides a bleach activator which is at least one macrocyclic manganese complex selected from the group consisting of [MnIII(rac-14-decane)X2]Y, [MnIII(mes-14-decane)X2]Y.H2O and [MnIII(mes-14-decane)X2]Y represented by Formulas 1-3, as well as a preparation method thereof. Also, the invention provides a bleaching composition and bleaching detergent composition comprising the bleach activator. The bleach activator comprising the manganese complex is used in a granulated form. wherein X is at least one selected from chlorine (—Cl) and acetate (—OOCCH3), and Y is an anion selected from Cl−, Br−, F−, NO3−, ClO4−, OH−, NCS−, N3−, and PF6−.

    Abstract translation: 本发明提供一种漂白活化剂，它是至少一种大环锰络合物，其选自[Mn III]（外消旋14-癸烷）X 2 Y，Y， [Mn III]（mes-14-癸烷）X 2 YH 2 O和[Mn III]（mes -14-癸烷）X 2] Y，以及其制备方法。 此外，本发明提供了一种漂白组合物和漂白洗涤剂组合物，其包含漂白活化剂。 包含锰络合物的漂白活化剂以颗粒形式使用。 其中X是选自氯（-Cl）和乙酸酯（-OOCCH 3））中的至少一种，Y是选自Cl - ， - ，，， 3， ，N - N，N 3 - ， - 和 - - - - - - - - - - - - - - - - - SUP> - 。

    Water leakage detecting device in dishwasher
    74.
    发明申请
    Water leakage detecting device in dishwasher 失效
    洗碗机中的漏水检测装置

    公开(公告)号：US20050028844A1

    公开(公告)日：2005-02-10

    申请号：US10882150

    申请日：2004-07-01

    Applicant: Yong Lee ,  Jae Lee ,  In Cho ,  Joung Kim

    Inventor： Yong Lee ,  Jae Lee ,  In Cho ,  Joung Kim

    IPC: A47L15/42 ,  G01M3/16 ,  G01M3/18 ,  F16K31/02 ,  B08B3/06 ,  F16K31/18

    CPC classification number: G01M3/16 ,  A47L15/421 ,  G01M3/186 ,  Y10T137/7358

    Abstract: A water leakage detecting device for effectively detecting water leakage and sensing malfunctions in the device is disclosed. The device includes a base retaining water leaked from a tub, a detector detecting whether leaked water is retained in the base, a first signal generator outputting a signal, when the detector detects the leaked water, a second signal generator outputting a signal, when the detector does not detect the leaked water, and a controller deciding whether to drain the leaked water and determining whether the water leakage detecting device has a malfunction.

    Abstract translation: 本发明公开了一种用于有效检测漏水和检测装置故障的漏水检测装置。 该装置包括保持从桶中泄漏的水的基座，检测在基座中是否保留漏水的检测器，当检测器检测到泄漏的水时输出信号的第一信号发生器，输出信号的第二信号发生器，当 检测器不检测泄漏的水，并且控制器决定是否排出泄漏的水并确定漏水检测装置是否具有故障。

    Method and circuit for testing a semiconductor memory device operating at high frequency
    75.
    发明授权
    Method and circuit for testing a semiconductor memory device operating at high frequency 失效
    用于测试高频工作的半导体存储器件的方法和电路

    公开(公告)号：US5933379A

    公开(公告)日：1999-08-03

    申请号：US52053

    申请日：1998-03-30

    Applicant: Churoo Park ,  Soo-In Cho

    Inventor： Churoo Park ,  Soo-In Cho

    IPC: G11C29/50 ,  G11C29/56 ,  G11C7/00

    CPC classification number: G11C29/50 ,  G11C29/56 ,  G11C11/401

    Abstract: A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.

    Abstract translation: 用于测试半导体存储器件的电路包括用于控制外部时钟信号的等待时间的等待时间控制器，用于在存储器件中产生列地址信号的内部列地址发生器和用于产生模式信号的模式寄存器。 用于测试半导体存储器件的电路还包括用于解码内部列地址发生器的输出地址信号的列地址解码器，用于读取或写入数据的存储单元，用于控制数据输入/输出的输入/输出控制单元 存储单元根据等待时间控制器的输出信号，数据输入缓冲器和数据输出缓冲器。 还提供了一种用于产生具有外部时钟信号频率“n”倍的内部时钟信号的倍频器。 通过提供上述改进，常规测试设备可用于测试高频存储器件。

    Wafer burn-in test circuit and a method thereof
    76.
    发明授权
    Wafer burn-in test circuit and a method thereof 失效
    晶片老化测试电路及其方法

    公开(公告)号：US5790465A

    公开(公告)日：1998-08-04

    申请号：US714577

    申请日：1996-09-16

    Applicant: Jae-gu Roh ,  Soo-in Cho

    Inventor： Jae-gu Roh ,  Soo-in Cho

    IPC: G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC classification number: G11C29/50 ,  G11C11/401 ,  G11C2029/5006 ,  G11C29/34

    Abstract: A burn-in test circuit of a semiconductor memory device with a first test circuit having output terminals connected to input terminals of a first half of plurality of word line drivers. A second test circuit has output terminals connected to input terminals of a second half of the plurality of word line drivers. The first and second tests circuits are sequentially activated to perform a burn-in test for all the memory cells.

    Abstract translation: 一种具有第一测试电路的半导体存储器件的老化测试电路，其具有连接到多个字线驱动器的前半部分的输入端的输出端子。 第二测试电路具有连接到多个字线驱动器的后半部分的输入端子的输出端子。 第一和第二测试电路被顺序激活，以对所有存储器单元执行老化测试。

    Semiconductor memory device having fast writing circuit for test thereof
    77.
    发明授权
    Semiconductor memory device having fast writing circuit for test thereof 失效
    具有用于测试的快速写入电路的半导体存储器件

    公开(公告)号：US5726939A

    公开(公告)日：1998-03-10

    申请号：US668952

    申请日：1996-06-24

    Applicant: Soo-In Cho ,  Jung-Hwa Lee

    Inventor： Soo-In Cho ,  Jung-Hwa Lee

    IPC: G11C11/401 ,  G11C8/12 ,  G11C29/00 ,  G11C29/34 ,  G11C13/00

    CPC classification number: G11C8/12

    Abstract: The time required for testing high-density semiconductor memory devices is reduced by circuits and methodology for rapidly writing test data bits into the memory array. A common word line enable signal is arranged to turn on all of the word lines in the array simultaneously. Test data bits are applied to the array by gating them onto the I/O lines so that separate test bit lines are not required. A fast test enable signal gates the test bits onto the I/O lines in all columns of the array simultaneously, so that all of the memory cells receive test bits at one time. The new circuitry has the further advantages of reduced area and capacitance, the latter further contributing to reducing the test data write time.

    Abstract translation: 通过用于将测试数据位快速写入存储器阵列的电路和方法来减少测试高密度半导体存储器件所需的时间。 公共字线使能信号被布置成同时打开阵列中的所有字线。 测试数据位通过将它们门控到I / O线上来应用于阵列，以便不需要单独的测试位线。 快速测试使能信号同时将测试位门控在阵列的所有列中的I / O线上，以便所有存储单元一次接收测试位。 新电路具有减小面积和电容的进一步优点，后者进一步有助于减少测试数据写入时间。

    SYSTEM AND METHOD FOR MANAGING RESOURCES IN A COMMUNICATION SYSTEM
    79.
    发明申请
    SYSTEM AND METHOD FOR MANAGING RESOURCES IN A COMMUNICATION SYSTEM 审中-公开
    在通信系统中管理资源的系统和方法

    公开(公告)号：US20130165136A1

    公开(公告)日：2013-06-27

    申请号：US13821736

    申请日：2011-09-09

    Applicant: Kyu-Min Kang ,  Sang-In Cho ,  Hyunduk Kang ,  Heon-Jin Hong ,  Chang-Joo Kim

    Inventor： Kyu-Min Kang ,  Sang-In Cho ,  Hyunduk Kang ,  Heon-Jin Hong ,  Chang-Joo Kim

    IPC: H04W16/14

    CPC classification number: H04W16/14

    Abstract: The present invention relates to a system and method for managing resources, which involve managing a plurality of frequency resources in a communication system including a plurality of systems not having rights to use a first frequency band. The system and method of the present invention involve: defining, upon the detection of a frequency band available to the plurality of systems from the first frequency band, an interface between objects in the available frequency band so as to enable coexistence and frequency-sharing among the plurality of systems in the available frequency band; defining a primitive of a service access point (SAP) which supports the transceiving of information belonging to the plurality of systems between the objects through the interface; enabling the objects to transceive information belonging to the plurality of systems through the interface using the primitive of the service access point; and enabling the plurality of systems to coexist and share a frequency in the available frequency band to use the available frequency band by transceiving the information belonging to the plurality of systems.

    Abstract translation: 本发明涉及一种用于管理资源的系统和方法，其涉及在包括不具有使用第一频带的权利的多个系统的通信系统中管理多个频率资源。 本发明的系统和方法包括：在检测到来自第一频带的多个系统可用的频带时，定义可用频带中的对象之间的接口，以便能够在可用频带内的共享和频率共享 在可用频带中的多个系统; 定义服务接入点（SAP）的原语，其支持通过接口在对象之间收集属于所述多个系统的信息; 使所述对象能够使用所述服务接入点的原语通过所述接口收发属于所述多个系统的信息; 并且使得所述多个系统能够共享和共享可用频带中的频率，以通过收发属于所述多个系统的信息来使用所述可用频带。

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