公开(公告)号：US20150340374A1

公开(公告)日：2015-11-26

申请号：US14642668

申请日：2015-03-09

Applicant: Won Seok JUNG ,  Joon Hee LEE ,  Keon Soo KIM ,  Sun Yeong LEE

Inventor： Won Seok JUNG ,  Joon Hee LEE ,  Keon Soo KIM ,  Sun Yeong LEE

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28008 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract translation: 一种制造存储器件的方法包括：提供衬底; 在单元区域中形成沿垂直于所述衬底的上表面的方向延伸的沟道;以及多个栅极电极层和多个绝缘层，所述绝缘层交替地堆叠在所述衬底上以与所述沟道相邻; 在设置在单元区域的外围的外围电路区域在基板上形成多个电路元件; 以及在所述单元区域和所述外围电路区域中的所述基板上形成层间绝缘层，所述层间绝缘层包括覆盖所述多个电路元件的第一，底部层间绝缘层和所述多个栅电极层的至少一部分， 以及设置在所述第一层间绝缘层上的第二顶层间绝缘层。

公开(公告)号：US09142715B2

公开(公告)日：2015-09-22

申请号：US13099127

申请日：2011-05-02

Applicant: Chang Youn Kim ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim ,  Hwa Mok Kim

Inventor： Chang Youn Kim ,  Joon Hee Lee ,  Jong Kyun You ,  Hong Chol Lim ,  Hwa Mok Kim

IPC: H01L33/00 ,  H01L33/10 ,  H01L33/02

CPC classification number: H01L33/10 ,  H01L33/025 ,  H01L2933/0091

Abstract: An exemplary embodiment of the present invention relates to a light emitting diode (LED) including a substrate, a first nitride semiconductor layer arranged on the substrate, an active layer arranged on the first nitride semiconductor layer, a second nitride semiconductor layer arranged on the active layer, a third nitride semiconductor layer disposed between the first nitride semiconductor layer or between the second nitride semiconductor layer and the active layer, the third nitride semiconductor layer comprising a plurality of scatter elements within the third nitride semiconductor layer, and a distributed Bragg reflector (DBR) comprising a multi-layered structure, the substrate being arranged between the DBR and the third nitride semiconductor layer.

Abstract translation: 本发明的示例性实施例涉及一种发光二极管（LED），其包括衬底，布置在衬底上的第一氮化物半导体层，布置在第一氮化物半导体层上的有源层，布置在有源层上的第二氮化物半导体层 层，设置在第一氮化物半导体层之间或第二氮化物半导体层和有源层之间的第三氮化物半导体层，在第三氮化物半导体层内包括多个散射元件的第三氮化物半导体层和分布式布拉格反射器 DBR），所述基板布置在所述DBR和所述第三氮化物半导体层之间。

公开(公告)号：US08986833B2

公开(公告)日：2015-03-24

申请号：US11816780

申请日：2005-05-27

Applicant: Joon-Hee Lee

Inventor： Joon-Hee Lee

IPC: B32B15/00 ,  C08G73/14 ,  C08F126/06 ,  C09J179/08 ,  H01B3/30

CPC classification number: C09J179/08 ,  C08G73/14 ,  H01B3/305 ,  H01B3/306 ,  Y10T428/2933 ,  Y10T428/2947

Abstract: Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost layer, has the increased adhesivity of the insulated coating layer to the conducting wire, as well as the excellent physical properties such as the wear resistance and flexibility, etc.

Abstract translation: 公开了用于搪瓷丝的搪瓷清漆组合物和使用其的搪瓷丝。 本发明涉及一种搪瓷丝的搪瓷清漆组合物，其中聚合物树脂组分包含在有机溶剂中，其中聚合物树脂组分包括第一聚酰胺酰亚胺树脂; 和具有聚酰胺酰亚胺的第二树脂，其中三嗪环被引入主链。 将这种涂料颜料组合物施加到最内层的搪瓷丝具有增加的绝缘涂层对导线的粘合性以及优异的物理性能如耐磨性和柔性等。

公开(公告)号：US08372711B2

公开(公告)日：2013-02-12

申请号：US13110113

申请日：2011-05-18

Applicant: Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

Inventor： Jong-Sun Sel ,  Jung-Dal Choi ,  Joon-Hee Lee ,  Hwa-Kyung Shin

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11529

Abstract: A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.

Abstract translation: 公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。 下导电图案在基板上。 绝缘图案位于下导电图案上。 上导电图案位于与下导电图案相对的绝缘图案上。 侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。 侧壁导电图形电连接上导电图案和下导电图案。 下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。 侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

公开(公告)号：US20130032871A1

公开(公告)日：2013-02-07

申请号：US13564117

申请日：2012-08-01

Applicant: Yoo-Cheol SHIN ,  Joon-Hee Lee

Inventor： Yoo-Cheol SHIN ,  Joon-Hee Lee

IPC: H01L29/788

CPC classification number: H01L21/764 ,  H01L27/11521

Abstract: A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.

Abstract translation: 半导体器件包括在衬底的有源区上的隧道绝缘层，隧道绝缘层上的浮动栅电极，衬底内的隔离沟槽，隔离沟槽限定有源区，使隧道绝缘层隔开，并隔离浮置栅电极 。 隔离沟槽的底部直接与衬底接触。 半导体器件还包括浮置栅电极上的下绝缘层，以及堆叠在下绝缘层上的中间绝缘层，上绝缘层和控制栅电极。 下绝缘层被配置为气密地密封隔离沟槽的顶部以限定和直接邻接隔离沟槽内的气隙。

公开(公告)号：US08329488B2

公开(公告)日：2012-12-11

申请号：US13506295

申请日：2012-04-10

Applicant: Chang Youn Kim ,  Shiro Sakai ,  Hwa Mok Kim ,  Joon Hee Lee ,  Soo Young Moon ,  Kyoung Wan Kim

Inventor： Chang Youn Kim ,  Shiro Sakai ,  Hwa Mok Kim ,  Joon Hee Lee ,  Soo Young Moon ,  Kyoung Wan Kim

IPC: H01L21/00

CPC classification number: H01L33/007 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L33/005 ,  H01L33/0079

Abstract: The present invention provides a method of fabricating a semiconductor substrate and a method of fabricating a light emitting device. The method includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a void is formed in a first portion of the first semiconductor layer under the metallic material layer during formation of the second semiconductor layer, and separating the substrate from the second semiconductor layer by etching at least a second portion of the first semiconductor layer using a chemical solution.

公开(公告)号：US20120272062A1

公开(公告)日：2012-10-25

申请号：US13090717

申请日：2011-04-20

Applicant: Joon-Hee LEE ,  Kwon-Soo CHANG

Inventor： Joon-Hee LEE ,  Kwon-Soo CHANG

IPC: H04L9/32 ,  G06F15/16

CPC classification number: G08C17/02 ,  G08C2201/40 ,  G08C2201/50 ,  G08C2201/93 ,  H04L12/282

Abstract: A method is provided for controlling a device by a portable terminal in a device automation system. Upon detecting an execution request for a single remote control mode for remotely controlling a device, the portable terminal sends a single remote control mode execution request message for requesting to execute the single remote control mode, to the device. Upon receiving from the device a single remote control mode execution response message being responsive to the single remote control mode execution request message, the portable terminal switches an operation mode thereof to the single remote control mode. Upon receiving from the device a device data message including device data output by the device, the portable terminal outputs the device data. Upon detecting a remote control command to remotely control the device while outputting the device data, the portable terminal sends a remote control message including the remote control command to the device.

Abstract translation: 提供了一种用于通过设备自动化系统中的便携式终端来控制设备的方法。 在检测到用于远程控制设备的单个远程控制模式的执行请求时，便携式终端向设备发送用于请求执行单个远程控制模式的单个远程控制模式执行请求消息。 在从设备接收到响应于单个远程控制模式执行请求消息的单个远程控制模式执行响应消息时，便携式终端将其操作模式切换到单个远程控制模式。 在从设备接收到包括由设备输出的设备数据的设备数据消息时，便携式终端输出设备数据。 当检测到远程控制命令以在输出设备数据的同时远程控制设备时，便携式终端向设备发送包括远程控制命令的遥控消息。

公开(公告)号：US08183075B2

公开(公告)日：2012-05-22

申请号：US13137124

申请日：2011-07-21

Applicant: Chang Youn Kim ,  Shiro Sakai ,  Hwa Mok Kim ,  Joon Hee Lee ,  Soo Young Moon ,  Kyoung Wan Kim

Inventor： Chang Youn Kim ,  Shiro Sakai ,  Hwa Mok Kim ,  Joon Hee Lee ,  Soo Young Moon ,  Kyoung Wan Kim

IPC: H01L21/00

CPC classification number: H01L33/007 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02491 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L33/005 ,  H01L33/0079

Abstract: The present invention provides a method of fabricating a semiconductor substrate and a method of fabricating a light emitting device. The method includes forming a first semiconductor layer on a substrate, forming a metallic material layer on the first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer and the metallic material layer, wherein a void is formed in a first portion of the first semiconductor layer under the metallic material layer during formation of the second semiconductor layer, and separating the substrate from the second semiconductor layer by etching at least a second portion of the first semiconductor layer using a chemical solution.

Abstract translation: 本发明提供一种制造半导体衬底的方法和一种制造发光器件的方法。 该方法包括在基板上形成第一半导体层，在第一半导体层上形成金属材料层，在第一半导体层和金属材料层上形成第二半导体层，在第一半导体层的第一部分形成空隙 在第二半导体层形成期间在金属材料层下面的第一半导体层，以及通过使用化学溶液蚀刻第一半导体层的至少第二部分来将衬底与第二半导体层分离。

公开(公告)号：US08169923B2

公开(公告)日：2012-05-01

申请号：US11528385

申请日：2006-09-28

Applicant: Joon-hee Lee ,  Ju-han Lee ,  Jun-hae Choi

Inventor： Joon-hee Lee ,  Ju-han Lee ,  Jun-hae Choi

IPC: H04L12/26

CPC classification number: H04B3/58 ,  H04B3/54 ,  H04B2203/5479 ,  H04B2203/5495

Abstract: A power line communication (PLC) method includes determining whether a destination communication apparatus to receive a data packet can directly communicate without using a repeater, transmitting the data packet to the destination communication apparatus when the destination communication apparatus can directly communicate without using the repeater, and transmitting the data packet to the repeater when the destination communication apparatus cannot directly communicate without using the repeater, and a power line communication (PLC) apparatus to perform the method.

Abstract translation: 电力线通信（PLC）方法包括确定接收数据分组的目的地通信装置是否可以直接通信而不使用中继器，当目的地通信装置可以直接通信而不使用中继器时，将数据分组发送到目的地通信装置， 以及当所述目的地通信装置不能直接通信而不使用所述中继器时，将所述数据分组发送到所述中继器，以及用于执行所述方法的电力线通信（PLC）装置。

公开(公告)号：US20120086506A1

公开(公告)日：2012-04-12

申请号：US13270384

申请日：2011-10-11

Applicant: Jeong-Ho LEE ,  Seung-Pyo HONG ,  Ju-Ho SON ,  Seung-Ho JANG ,  Hyun-Tae GILL ,  Joon-Hee LEE ,  Yi-Ju ROH

Inventor： Jeong-Ho LEE ,  Seung-Pyo HONG ,  Ju-Ho SON ,  Seung-Ho JANG ,  Hyun-Tae GILL ,  Joon-Hee LEE ,  Yi-Ju ROH

IPC: H03H11/02

CPC classification number: H03K19/00384

Abstract: An electronic circuit apparatus for compensating for a process variation of a resistor in an electronic circuit is provided. The electronic circuit includes a detecting part for generating a tune voltage corresponding to a process variation value of the at least one resistor, and a compensating part for compensating for a process variation of the at least one resistor using the tune voltage.

Abstract translation: 提供了用于补偿电子电路中的电阻器的工艺变化的电子电路装置。 电子电路包括用于产生对应于至少一个电阻器的过程变化值的调谐电压的检测部分和用于使用调谐电压来补偿至少一个电阻器的工艺变化的补偿部分。