公开(公告)号：USD530695S1

公开(公告)日：2006-10-24

申请号：US29241754

申请日：2005-10-31

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：USD687430S1

公开(公告)日：2013-08-06

申请号：US29422594

申请日：2012-05-22

Applicant: Jung-Hyun Park ,  Jae-Seung Song ,  Dong-Seok Lee

Designer： Jung-Hyun Park ,  Jae-Seung Song ,  Dong-Seok Lee

公开(公告)号：US08416738B2

公开(公告)日：2013-04-09

申请号：US12895190

申请日：2010-09-30

Applicant: Won Jae Shin ,  Young Jun Hong ,  Jung Hyun Park ,  Chang Yong Shin ,  Dong Jo Park

Inventor： Won Jae Shin ,  Young Jun Hong ,  Jung Hyun Park ,  Chang Yong Shin ,  Dong Jo Park

IPC: H04W4/00

CPC classification number: H04B7/024

Abstract: A communication method for at least one mobile station that includes a target mobile station that performs a Cooperative Multi-Point (CoMP) communication with at least two base stations, is provided. The communication method includes determining a beamforming vector used by the at least two base stations based on channel vectors and at least one channel matrix such that a signal-to-leakage-plus-noise-ratio (SLNR) for a target antenna from among antennas of a target mobile station is maximized. A Cholesky factorization may be used to determine an optimal beamforming vector with a low complexity.

Abstract translation: 提供一种用于至少一个移动站的通信方法，该移动站包括与至少两个基站进行协作多点（CoMP）通信的目标移动站。 通信方法包括基于信道向量和至少一个信道矩阵确定由至少两个基站使用的波束成形向量，使得从天线中的目标天线的信号与泄漏加噪声比（SLNR） 目标移动台的最大化。 可以使用Cholesky因式分解来确定具有低复杂度的最优波束形成向量。

公开(公告)号：US20120244662A1

公开(公告)日：2012-09-27

申请号：US13491279

申请日：2012-06-07

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

IPC: H01L21/50

CPC classification number: H05K3/00 ,  H01L2224/16225 ,  H05K3/30 ,  Y10T29/49124

Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component.

Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，片上封装衬底上的单层板包括形成在绝缘体上表面上的绝缘体，电路图案和倒装焊接焊盘，导体凸块， 与电路图案的下表面接触并穿透绝缘体，阻焊层，其形成在绝缘体的上表面上，使得至少一部分倒装芯片接合焊盘露出，并且 倒装芯片焊接凸块，其形成在倒装焊盘的上表面上，以便与电子部件进行倒装芯片连接。

公开(公告)号：US08197702B2

公开(公告)日：2012-06-12

申请号：US12508224

申请日：2009-07-23

Applicant: Myung-Sam Kang ,  Jung-Hyun Park ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Jung-Hyun Park ,  Ji-Eun Kim

IPC: C25D5/02 ,  B32B37/00 ,  B32B38/00

CPC classification number: B32B37/02 ,  B32B2457/08 ,  C25D5/022 ,  H05K3/205 ,  H05K3/428 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/0384

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for interlayer connection can include forming a circuit pattern on one side of a carrier, pressing one side of the carrier into one side of the insulator, removing the carrier, forming a hole penetrating through the insulator by processing one end of the circuit pattern, and forming a conductive material inside the hole to have the conductive material correspond to the via.

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于层间连接的通孔的印刷电路板的方法可以包括在载体的一侧上形成电路图案，将载体的一侧压在绝缘体的一侧，去除载体，形成贯穿该载体的孔 通过处理电路图案的一端，并且在孔内形成导电材料以使导电材料对应于通孔。

公开(公告)号：US20110260234A1

公开(公告)日：2011-10-27

申请号：US13172578

申请日：2011-06-29

Applicant: Jung-Hyun PARK ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

Inventor： Jung-Hyun PARK ,  Jung-Geun Jee ,  Hyoeng-Ki Kim ,  Yong-Woo Hyung ,  Won-Jun Jang

IPC: H01L29/788

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A semiconductor device may include a tunnel insulating layer disposed on an active region of a substrate, field insulating patterns disposed in surface portions of the substrate to define the active region, each of the field insulating patterns having an upper recess formed at an upper surface portion thereof, a stacked structure disposed on the tunnel insulating layer, and impurity diffusion regions disposed at surface portions of the active region adjacent to the stacked structure.

Abstract translation: 半导体器件可以包括设置在衬底的有源区上的隧道绝缘层，设置在衬底的表面部分中以限定有源区的场绝缘图案，每个场绝缘图案具有形成在上表面部分的上凹部 设置在隧道绝缘层上的堆叠结构，以及设置在与堆叠结构相邻的有源区的表面部分处的杂质扩散区。

公开(公告)号：US20100255634A1

公开(公告)日：2010-10-07

申请号：US12801574

申请日：2010-06-15

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A manufacturing method of bottom substrate of package. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.

Abstract translation: 封装底部基板的制造方法。 封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体 层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量 安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是 可能在顶部基板和底部基板之间。

公开(公告)号：US07802358B2

公开(公告)日：2010-09-28

申请号：US12453832

申请日：2009-05-22

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H05K3/00

CPC classification number: H05K3/4691 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K1/189 ,  H05K3/4623 ,  H05K2201/055 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/063 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Abstract translation: 一种刚性柔性多层印刷电路板的制造方法，包括：柔性基板，其两侧形成有可弯曲的电路; 层叠在柔性基板上的刚性基板和电路形成在两侧，并且形成有安装半导体芯片的空腔; 以及粘合柔性基板和刚性基板并具有绝缘性的粘合片。 当安装相同数量的半导体芯片或实施POP时，封装的整体厚度可以更低。 此外，可以使用空间作为芯层的厚度来安装另外两个半导体芯片，并且可以实现当传统技术中安装在底部基板上的半导体芯片的数量变为二倍时的结构是不可能的。

公开(公告)号：USD614221S1

公开(公告)日：2010-04-20

申请号：US29315535

申请日：2009-07-02

Applicant: Jung-Hyun Park

Designer： Jung-Hyun Park

公开(公告)号：US20100018633A1

公开(公告)日：2010-01-28

申请号：US12408366

申请日：2009-03-20

Applicant: Myung-Sam KANG ,  Jung-Hyun PARK ,  Jeong-Woo PARK ,  Ji-Eun KIM

Inventor： Myung-Sam KANG ,  Jung-Hyun PARK ,  Jeong-Woo PARK ,  Ji-Eun KIM

IPC: B32B37/00

CPC classification number: B32B38/04 ,  B32B38/10 ,  B32B2038/0092 ,  B32B2038/047 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1064 ,  Y10T156/1082

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于将一层连接到另一层的通路的印刷电路板的制造方法可以包括在载体的一个表面上形成电路图案; 在载体的一个表面上处理与通孔对应的孔; 将载体的表面压缩到绝缘体的一个表面中; 移除载体; 处理绝缘体上的通孔，对应于孔的位置; 并且在通孔中形成导电材料，从而容易地加工用于形成通孔的孔，并且具有高的设计自由度