公开(公告)号：US06658763B2

公开(公告)日：2003-12-09

申请号：US10292396

申请日：2002-11-12

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: F26B504

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate are provided. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.

Abstract translation: 提供了一种用于加热和冷却衬底的方法和装置。 提供了一种室，其包括适于加热位于加热机构附近的基板的加热机构，与加热机构间隔开并适于冷却位于冷却机构附近的基板的冷却机构，以及适于将基板 靠近加热机构的位置和靠近冷却机构的位置。

公开(公告)号：US06645550B1

公开(公告)日：2003-11-11

申请号：US09599125

申请日：2000-06-22

Applicant: Robin Cheung ,  Yezdi Dordi ,  Jennifer Tseng

Inventor： Robin Cheung ,  Yezdi Dordi ,  Jennifer Tseng

IPC: B05D102

CPC classification number: H01L21/76849 ,  H01L21/288 ,  Y10S134/902

Abstract: A method of treating a substrate. The method comprises forming a metal-containing layer on at least a selected portion of the substrate during a substrate cleaning process.

Abstract translation: 一种处理基材的方法。 该方法包括在衬底清洗过程中在衬底的至少一部分选择部分上形成含金属层。

公开(公告)号：US06258223B1

公开(公告)日：2001-07-10

申请号：US09350877

申请日：1999-07-09

Applicant: Robin Cheung ,  Daniel A. Carl ,  Yezdi Dordi ,  Peter Hey ,  Ratson Morad ,  Liang-Yuh Chen ,  Paul F. Smith ,  Ashok K. Sinha

Inventor： Robin Cheung ,  Daniel A. Carl ,  Yezdi Dordi ,  Peter Hey ,  Ratson Morad ,  Liang-Yuh Chen ,  Paul F. Smith ,  Ashok K. Sinha

IPC: C25D1700

CPC classification number: H01L21/68721 ,  C25D7/123 ,  C25D17/001 ,  H01L21/68728 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a system that provides for electroless deposition performed in-situ with an electroplating process to minimize oxidation and other contaminants prior to the electroplating process. The system allows the substrate to be transferred from the electroless deposition process to the electroplating process with a protective coating to also minimize oxidation. The system generally includes a mainframe having a mainframe substrate transfer robot, a loading station disposed in connection with the mainframe, one or more processing facilities disposed in connection with the mainframe, an electroless supply fluidly connected to the one or more processing applicators and optionally includes a spin-rinse-dry (SRD) station, a rapid thermal anneal chamber and a system controller for controlling the deposition processes and the components of the electro-chemical deposition system.

Abstract translation: 本发明公开了一种系统，其提供用电镀方法原位进行的无电沉积，以在电镀过程之前使氧化和其它污染物最小化。 该系统允许基板由无电镀沉积工艺转移到具有保护涂层的电镀工艺中以使氧化最小化。 该系统通常包括具有主机基板传送机器人的主机，与主机连接设置的加载站，与主机连接设置的一个或多个处理设备，流体连接到该一个或多个处理施加器的无电解供应器，并且可选地包括 旋转干燥（SRD）站，快速热退火室和用于控制沉积过程和电化学沉积系统的组件的系统控制器。

公开(公告)号：US06258220B1

公开(公告)日：2001-07-10

申请号：US09289074

申请日：1999-04-08

Applicant: Yezdi Dordi ,  Donald J. Olgado ,  Ratson Morad ,  Peter Hey ,  Mark Denome ,  Michael Sugarman ,  Mark Lloyd ,  Joseph Stevens ,  Dan Marohl ,  Ho Seon Shin ,  Eugene Ravinovich ,  Robin Cheung ,  Ashok K. Sinha ,  Avi Tepman ,  Dan Carl ,  George Birkmaier

Inventor： Yezdi Dordi ,  Donald J. Olgado ,  Ratson Morad ,  Peter Hey ,  Mark Denome ,  Michael Sugarman ,  Mark Lloyd ,  Joseph Stevens ,  Dan Marohl ,  Ho Seon Shin ,  Eugene Ravinovich ,  Robin Cheung ,  Ashok K. Sinha ,  Avi Tepman ,  Dan Carl ,  George Birkmaier

IPC: C25D1700

CPC classification number: H01L21/6723 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06 ,  C25D21/02 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/67028 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67126 ,  H01L21/67167 ,  H01L21/67184 ,  H01L21/67745 ,  H01L21/68707 ,  H01L21/68721 ,  H01L21/68728 ,  H01L21/68742 ,  H05K3/241

Abstract: The present invention provides an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. The electro-chemical deposition system generally comprises a mainframe having a mainframe wafer transfer robot, a loading station disposed in connection with the mainframe, one or more processing cells disposed in connection with the mainframe, and an electrolyte supply fluidly connected to the one or more electrical processing cells. Preferably, the electro-chemical deposition system includes a spin-rinse-dry (SRD) station disposed between the loading station and the mainframe, a rapid thermal anneal chamber attached to the loading station, and a system controller for controlling the electro-chemical deposition process and the components of the electro-chemical deposition system.

Abstract translation: 本发明提供了一种电化学沉积系统，其被设计成具有可扩展以适应未来设计和间隙填充要求的柔性结构，并提供令人满意的生产量以满足其它处理系统的需求。 电化学沉积系统通常包括具有主机晶片传送机器人的主机，与主机连接设置的加载站，与主机连接设置的一个或多个处理单元，以及流体连接到该主机的一个或多个 电加工电池。 优选地，电化学沉积系统包括设置在加载站和主机之间的旋转干燥（SRD）站，附接到装载站的快速热退火室，以及用于控制电化学沉积的系统控制器 工艺和电化学沉积系统的组件。

公开(公告)号：US06200913B1

公开(公告)日：2001-03-13

申请号：US09191040

申请日：1998-11-12

Applicant: Lu You ,  Simon S. Chan ,  John Iacoponi ,  Richard J. Huang ,  Robin Cheung

Inventor： Lu You ,  Simon S. Chan ,  John Iacoponi ,  Richard J. Huang ,  Robin Cheung

IPC: H01L21324

CPC classification number: H01L21/02134 ,  H01L21/02282 ,  H01L21/31058 ,  H01L21/3124

Abstract: This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.

Abstract translation: 本发明包括改进旋涂电介质层固化的方式。 半导体晶片被涂覆有用于旋涂电介质材料的前体，并且在溶液变薄并均匀之后，将晶片放置在固化炉中，任选地包含惰性气体，并预热到低于该温度的温度 在半导体晶片中不产生热机械应力和/或氧化。 然后将固化炉内的温度升高至固化温度，然后缓慢降低温度，以防止形成应力裂纹和薄膜的介电功能的损失。 本发明的固化方法可用于制造采用各种旋涂材料的半导体器件。

公开(公告)号：US5776834A

公开(公告)日：1998-07-07

申请号：US478315

申请日：1995-06-07

Applicant: Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

Inventor： Steven Avanzino ,  Darrell M. Erb ,  Robin Cheung ,  Rich Klein ,  Pervaiz Sultan

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/471

CPC classification number: H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/7682 ,  H01L21/76837 ,  H01L23/5222 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with void free insulating material with a dielectric constant of greater than about 3.5.

公开(公告)号：US5688717A

公开(公告)日：1997-11-18

申请号：US565308

申请日：1995-11-30

Applicant: Lewis Shen ,  Sheshadri Ramaswami ,  Mark Chang ,  Robin Cheung

Inventor： Lewis Shen ,  Sheshadri Ramaswami ,  Mark Chang ,  Robin Cheung

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/532 ,  H01L21/28

CPC classification number: H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

公开(公告)号：US5646448A

公开(公告)日：1997-07-08

申请号：US699821

申请日：1996-08-19

Applicant: Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.

Abstract translation: 多层半导体结构包括导电通孔。 导电通孔包括具有高抗电迁移性的金属颗粒。 沉淀物由沉积在通孔上的铜或金的保形层制成，以形成位于通孔中的铜或金储存器或触点。 在储存器和绝缘层之间设置阻挡层以防止颗粒扩散到绝缘层中。 颗粒可以通过选择性沉积或通过蚀刻保形层形成。 可以通过溅射，准直溅射，化学气相沉积（CVD），浸渍，蒸发或其它方式沉积共形层。 可以通过各向异性干蚀刻，等离子体辅助蚀刻或其它层去除技术来蚀刻阻挡层和颗粒。

公开(公告)号：US5635423A

公开(公告)日：1997-06-03

申请号：US320516

申请日：1994-10-11

Applicant: Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

Inventor： Richard J. Huang ,  Angela Hui ,  Robin Cheung ,  Mark Chang ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/7681 ,  H01L21/76807 ,  H01L21/76813

Abstract: A semiconductor device containing an interconnection structure having a reduced interwiring spacing is produced by a modified dual damascene process. In one embodiment, an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etch stop layer therebetween. A larger opening for a trench is then formed in the second insulative layer while simultaneously extending the via opening through the etch stop layer and first insulative layer. The trench and via are then simultaneously filled with conductive material.

Abstract translation: 通过改进的双镶嵌工艺产生包含具有减小的布线间距的互连结构的半导体器件。 在一个实施例中，用于通孔的开口最初形成在第一绝缘层之上的第二绝缘层中，其间具有蚀刻停止层。 然后在第二绝缘层中形成用于沟槽的较大开口，同时使通孔开口延伸穿过蚀刻停止层和第一绝缘层。 沟槽和通孔然后同时填充导电材料。