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    Non-volatile memory with tier-wise ramp down after program-verify
    71.
    发明授权
    Non-volatile memory with tier-wise ramp down after program-verify 有权

    公开(公告)号：US11972820B2

    公开(公告)日：2024-04-30

    申请号：US17898850

    申请日：2022-08-30

    Applicant: SanDisk Technologies LLC

    Inventor： Jiacen Guo ,  Dengtao Zhao ,  Xiang Yang

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102

    Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.

    Recovery pulses to counter cumulative read disturb
    74.
    发明授权
    Recovery pulses to counter cumulative read disturb 有权

    公开(公告)号：US11972808B2

    公开(公告)日：2024-04-30

    申请号：US17666940

    申请日：2022-02-08

    Applicant: SanDisk Technologies LLC

    Inventor： Abhijith Prakash ,  Xiang Yang

    IPC: G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

    CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  H10B41/27 ,  H10B43/27

    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes organized in rows grouped in strings and configured to retain a threshold voltage. The memory cells are connected in series between a drain-side select gate transistor on a drain-side of each of the memory holes and a source-side select gate transistor on a source-side of each of the memory holes. A control means determines whether a downshift recovery trigger event has occurred in memory operations. In response to determining the downshift recovery trigger event has occurred, the control means inserts at least one of a predetermined idle time in the memory operations and a recovery pulse of a negative voltage to the drain-side select gate transistor of the memory holes of the strings for a predetermined pulse period of time during one of the memory operations.

    Cross-point array refresh scheme
    75.
    发明授权
    Cross-point array refresh scheme 有权

    公开(公告)号：US11972787B2

    公开(公告)日：2024-04-30

    申请号：US17824806

    申请日：2022-05-25

    Applicant: SanDisk Technologies LLC

    Inventor： Michael Nicolas Albert Tran ,  Michael K. Grobis ,  Ward Parkinson ,  Nathan Franklin

    IPC: G06F11/10 ,  G11C11/16

    CPC classification number: G11C11/1659 ,  G06F11/1044 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

    Abstract: Technology is disclosed herein for refreshing threshold switching selectors in programmable resistance memory cells in cross-point memory arrays. The Vt of the threshold switching selector may drift over time. The memory system resets the Vt of the threshold switching selectors with a selector refresh operation and uses a separate data refresh operation to refresh data in programmable resistance memory elements. The data refresh operation itself may also refresh the selector. However, the threshold switching selector refresh operation is faster than the data refresh operation. Moreover, the selector refresh operation consumes much less power and/or current then the data refresh operation. The selector refresh operation may thus be performed at a higher rate than the data refresh operation.

    Three-dimensional memory device with replacement select gate electrodes and methods of manufacturing the same
    78.
    发明授权
    Three-dimensional memory device with replacement select gate electrodes and methods of manufacturing the same 有权

    公开(公告)号：US11968827B2

    公开(公告)日：2024-04-23

    申请号：US17465131

    申请日：2021-09-02

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Tatsuya Hinoue

    IPC: H10B41/27 ,  H01L29/792 ,  H10B43/27

    CPC classification number: H10B41/27 ,  H01L29/7926 ,  H10B43/27

    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. The sacrificial material layers include a stack of word-line-level sacrificial material layers and at least one drain-select-level sacrificial material layer. Drain-select-level openings are formed through the at least one drain-select-level sacrificial material layer, which is replaced with at least one drain-select-level electrically conductive layer. Memory openings are formed by vertically extending the drain-select-level openings through the word-line-level sacrificial material layers. Memory opening fill structures are formed within the memory openings. The word-line-level sacrificial material layers are replaced with word-line-level electrically conductive layers.

    Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same
    79.
    发明授权
    Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same 有权

    公开(公告)号：US11968825B2

    公开(公告)日：2024-04-23

    申请号：US17126504

    申请日：2020-12-18

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Zhen Chen ,  Yanli Zhang

    IPC: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    CPC classification number: H10B41/27 ,  G11C8/14 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures including a respective vertical semiconductor channel and a respective memory film vertically extend through the alternating stack and the vertical layer stack. Each of the vertical semiconductor channels includes a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack.

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