公开(公告)号：US06489223B1

公开(公告)日：2002-12-03

申请号：US09898949

申请日：2001-07-03

Applicant: Terence B. Hook ,  Randy W. Mann

Inventor： Terence B. Hook ,  Randy W. Mann

IPC: H01L21425

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66659 ,  H01L29/7835

Abstract: Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the structure. Other structures have no barrier or have two barriers. Source and drain engineering can be performed for LDD, halo, and other desired implants.

Abstract translation: 不同的对称和非对称装置在同一芯片上使用非关键块掩模和成角度的植入物形成。 选择性地在结构的一侧形成势垒，并且该势垒阻挡以一定角度朝向该结构注入的掺杂剂。 其他结构没有障碍或有两个障碍。 可以对LDD，光晕和其他所需的植入物进行源和漏极工程。

公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

Applicant: John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

Inventor： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC: G11C700

CPC classification number: G11C8/08 ,  G11C11/418 ,  H01L27/11

Abstract: A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

Abstract translation: 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。

公开(公告)号：US06256755B1

公开(公告)日：2001-07-03

申请号：US09174789

申请日：1998-10-19

Applicant: Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

Inventor： Terence B. Hook ,  Chung H. Lam ,  Eric S. Lee ,  James S. Nakos ,  Nivo Rovedo ,  Richard Q. Williams ,  Robert C. Wong

IPC: G11C2900

CPC classification number: G11C16/349 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/50012

Abstract: An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

Abstract translation: 一种用于检测NVRAM单元的不良阵列的装置和方法。 在常规擦除功能期间提供计数器，其为NVRAM单元的擦除时间间隔。 计算的擦除间隔与最大擦除间隔进行比较，以确定至少第一特性，其指示NVRAM的块处于其使用寿命的结束。 通过计算擦除时间函数中的斜率与模拟擦除函数的数量来确定第二特性。 当擦除功能的斜率超过最大斜率时，NVRAM阵列被确定为其使用寿命结束。

公开(公告)号：US5972765A

公开(公告)日：1999-10-26

申请号：US895049

申请日：1997-07-16

Applicant: William F. Clark ,  Thomas G. Ference ,  Terence B. Hook ,  Dale W. Martin

Inventor： William F. Clark ,  Thomas G. Ference ,  Terence B. Hook ,  Dale W. Martin

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336

CPC classification number: H01L21/28211 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/665 ,  H01L29/66575

Abstract: Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

Abstract translation: 形成半导体器件的膜的方法，其中在形成膜期间提供包含氘化物质的源材料。

公开(公告)号：US5562770A

公开(公告)日：1996-10-08

申请号：US343152

申请日：1994-11-22

Applicant: Bomy A. Chen ,  Terence B. Hook ,  Subhash B. Kulkarni

Inventor： Bomy A. Chen ,  Terence B. Hook ,  Subhash B. Kulkarni

IPC: H01L21/205 ,  C30B25/18 ,  H01L21/8249 ,  H01L27/06

CPC classification number: C30B25/18 ,  Y10S438/938

Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.

Abstract translation: 本发明提供了一种全局应力修饰的方法，其导致半导体衬底上的外延生长的半导体器件层中的位错数目，其中器件层和衬底具有晶格失配。 本发明教导了一种通过从衬底的背面移除薄膜层或者添加薄膜层而向衬底赋予凸曲率的方法，以便在器件层中实现位错密度的降低。

公开(公告)号：US08619979B2

公开(公告)日：2013-12-31

申请号：US12823278

申请日：2010-06-25

Applicant: Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

Inventor： Joel T. Ficke ,  William E. Hall ,  Terence B. Hook ,  Michael A. Sperling ,  Larry Wissel

IPC: G06F21/73 ,  H04L9/08

CPC classification number: G06F21/73 ,  H04L9/08 ,  H04L9/0866 ,  H04L9/3278

Abstract: Electronic devices and methods are disclosed to provide and to test a physically unclonable function (PUF) based on relative threshold voltages of one or more pairs of transistors. In a particular embodiment, an electronic device is operable to generate a response to a challenge. The electronic device includes a plurality of transistors, with each of the plurality of transistors having a threshold voltage substantially equal to an intended threshold voltage. The electronic device includes a challenge input configured to receive the challenge. The challenge input includes one or more bits that are used to individually select each of a pair of transistors of the plurality of transistors. The electronic device also includes a comparator to receive an output voltage from each of the pair of transistors and to generate a response indicating which of the pair of transistors has the higher output voltage. The output voltage of each of the pair of transistors varies based on the threshold voltage of each of the pair of transistors.

Abstract translation: 公开了电子装置和方法，以基于一对或多对晶体管的相对阈值电压来提供和测试物理上不可克隆的功能（PUF）。 在特定实施例中，电子设备可操作以产生对挑战的响应。 电子设备包括多个晶体管，多个晶体管中的每一个具有基本上等于预期阈值电压的阈值电压。 电子设备包括被配置为接收挑战的挑战输入。 挑战输入包括用于单独选择多个晶体管中的一对晶体管中的每一个的一个或多个位。 该电子设备还包括一个比较器，用于接收来自该对晶体管中的每一个的输出电压，并产生一个响应，该响应指示该对晶体管中的哪一个具有较高的输出电压。 该对晶体管中的每一个晶体管的输出电压根据该晶体管对的阈值电压而变化。

公开(公告)号：US20130256748A1

公开(公告)日：2013-10-03

申请号：US13431414

申请日：2012-03-27

Applicant: William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

Inventor： William F. Clark, JR. ,  Robert J. Gauthier, JR. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

IPC: H01L29/73 ,  G06F17/50 ,  H01L21/331

CPC classification number: H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

Abstract: Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

Abstract translation: 无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

公开(公告)号：US08513106B2

公开(公告)日：2013-08-20

申请号：US12964082

申请日：2010-12-09

Applicant: Terence B. Hook

Inventor： Terence B. Hook

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/78648

Abstract: Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.

公开(公告)号：US20120299080A1

公开(公告)日：2012-11-29

申请号：US13114283

申请日：2011-05-24

Applicant: Robert H. Dennard ,  Terence B. Hook

Inventor： Robert H. Dennard ,  Terence B. Hook

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84

Abstract: A structure includes a semiconductor substrate having a first type of conductivity and a top surface; an insulating layer disposed over the top surface; a semiconductor layer disposed over the insulating layer and a plurality of transistor devices disposed upon the semiconductor layer. Each transistor device includes a source, a drain and a gate stack defining a channel between the source and the drain, where some transistor devices have a first type of channel conductivity and the remaining transistor devices have a second type of channel conductivity. The structure further includes a well region formed adjacent to the top surface of the substrate and underlying the plurality of transistor devices, the well region having a second type of conductivity and extending to a first depth within the substrate. The structure further includes first isolation regions between adjacent transistor devices and extending through the semiconductor layer to a depth sufficient for electrically isolating the adjacent transistor devices from one another, and second isolation regions between selected adjacent transistor devices. The second isolation regions extend through the silicon layer, through the insulating layer and into the substrate to a second depth that is greater than the first depth to electrically separate the well region into a first well region and a second well region. The structure further includes at least one back gate region disposed wholly within a well region and underlying one of the plurality of transistor devices, the at least one back gate region has the first type of conductivity and is electrically floating within the well region, where during operation the at least one back gate region having the first type of conductivity is biased by leakage and capacitive coupling by a bias potential applied to the well region within which it is disposed.

Abstract translation: 一种结构包括具有第一类导电性的半导体衬底和顶表面; 设置在所述顶表面上的绝缘层; 设置在所述绝缘层上的半导体层和设置在所述半导体层上的多个晶体管器件。 每个晶体管器件包括源极，漏极和限定在源极和漏极之间的沟道的栅极堆叠，其中一些晶体管器件具有第一类型的沟道导电性，并且剩余的晶体管器件具有第二类型的沟道导电性。 所述结构还包括邻近所述衬底的顶表面形成并位于所述多个晶体管器件下方的阱区，所述阱区具有第二类型的导电性并延伸到所述衬底内的第一深度。 该结构还包括相邻晶体管器件之间的第一隔离区域，并延伸穿过半导体层至足以将相邻晶体管器件彼此电绝缘的深度以及所选择的相邻晶体管器件之间的第二隔离区域。 第二隔离区延伸穿过硅层，穿过绝缘层并进入衬底至比第一深度更大的第二深度，以将阱区电分离成第一阱区和第二阱区。 该结构还包括至少一个背栅极区域，其完全设置在阱区域内并且位于多个晶体管器件中的一个之下，所述至少一个背栅极区域具有第一类型的导电性并且在阱区域内电浮动， 操作具有第一类型的导电性的至少一个背栅极区域被施加到其所配置的阱区域的偏置电位的泄漏和电容耦合偏置。

公开(公告)号：US08230586B2

公开(公告)日：2012-07-31

申请号：US11848263

申请日：2007-08-31

Applicant: Douglas D Coolbaugh ,  Ebenezer E Eshun ,  Terence B Hook ,  Robert M Rassel ,  Edmund J Sprogis ,  Anthony K Stamper ,  William J Murphy

Inventor： Douglas D Coolbaugh ,  Ebenezer E Eshun ,  Terence B Hook ,  Robert M Rassel ,  Edmund J Sprogis ,  Anthony K Stamper ,  William J Murphy

IPC: H01C7/02 ,  H01C7/04

CPC classification number: H01C7/1013 ,  H01C1/084 ,  H01L2924/0002 ,  Y10T29/49083 ,  Y10T29/49085 ,  Y10T29/49099 ,  Y10T29/49144 ,  Y10T29/49147 ,  H01L2924/00

Abstract: A method of cooling a resistor is provided. The method includes forming a first electrical insulator having a high thermal conductivity in thermal contact with an electrically resistive pathway and forming a substrate adjacent the electrical insulator. The method further includes forming a first electrical conductor having a high thermal conductivity within the second substrate and in thermal contact with the electrical insulator.

Abstract translation: 提供一种冷却电阻器的方法。 该方法包括形成具有与电阻通路热接触的高热导率的第一电绝缘体，并形成邻近电绝缘体的衬底。 该方法还包括在第二衬底内形成具有高导热性并与电绝缘体热接触的第一电导体。