公开(公告)号：US20240068097A1

公开(公告)日：2024-02-29

申请号：US18452725

申请日：2023-08-21

Applicant: ASM IP Holding B.V.

Inventor： Subir Parui ,  Werner Knaepen ,  Dieter Pierreux ,  Kelly Houben ,  Herbert Terhorst ,  Theodorus G.M. Oosterlaken ,  Angelos Karagiannis

IPC: C23C16/455 ,  C23C16/44 ,  C23C16/458 ,  C23C16/52

CPC classification number: C23C16/45574 ,  C23C16/4412 ,  C23C16/45546 ,  C23C16/4584 ,  C23C16/52

Abstract: A substrate processing apparatus configured to from a layer on a plurality of substrates is disclosed. Embodiments of the presently described substrate processing apparatus comprise a process chamber. The process chamber comprises process space for receiving a substrate boat arranged for holding the plurality of substrates. The substrate processing apparatus further comprise a gas delivery assembly comprising at least one gas injector; a gas exhaust assembly comprising two gas outlets. The two gas outlets are positioned at a distance on either side of the at least one gas injector.

公开(公告)号：US11898243B2

公开(公告)日：2024-02-13

申请号：US17113301

申请日：2020-12-07

Applicant: ASM IP Holding B.V.

Inventor： Pia Homm Jara ,  Werner Knaepen ,  Dieter Pierreux ,  Bert Jongbloed ,  Panagiota Arnou ,  Ren-Jie Chang ,  Qi Xie ,  Giuseppe Alessio Verni ,  Gido van der Star

IPC: C23C16/34 ,  H01L21/285 ,  C23C16/44 ,  C23C16/56 ,  C23C16/455 ,  C23C16/04

CPC classification number: C23C16/34 ,  C23C16/04 ,  C23C16/4408 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/56 ,  H01L21/28568

Abstract: Methods of forming a vanadium nitride-containing layer comprise providing a substrate within a reaction chamber of a reactor and depositing a vanadium nitride-containing layer onto a surface of the substrate, wherein the deposition process comprises providing a vanadium precursor to the reaction chamber and providing a nitrogen precursor to the reaction chamber.

公开(公告)号：US20240044003A1

公开(公告)日：2024-02-08

申请号：US18362404

申请日：2023-07-31

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Bert Jongbloed ,  Didem Ernur

IPC: C23C16/458 ,  H01L21/3205

CPC classification number: C23C16/4583 ,  H01L21/32055 ,  C23C16/4581

Abstract: A wafer boat and a method for forming a layer on a plurality of substrates that are provided in the wafer boat is disclosed. Aspects of the presently described wafer boat comprise at least two wafer boat rods, each of which including at least a first set of slots for holding a plurality of substrates. The wafer boat further includes a plurality of plates, whereby at least one slot of the at least first set of slots is provided in between two neighboring plates.

公开(公告)号：US20230360905A1

公开(公告)日：2023-11-09

申请号：US18312019

申请日：2023-05-04

Applicant: ASM IP Holding, B.V.

Inventor： Werner Knaepen ,  Arjen Klaver ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L21/02 ,  C23C16/455

CPC classification number: H01L21/0217 ,  C23C16/45544 ,  C23C16/45553 ,  C23C16/45574 ,  H01L21/02211 ,  H01L21/0228

Abstract: A method for forming a silicon-comprising layer on a substrate may comprise providing the substrate to a process chamber, the process chamber being comprised in a low pressure chemical vapor deposition (LPCVD) furnace. A repetitive deposition cycle is performed. The deposition cycle comprises a first deposition pulse and a second deposition pulse comprising a provision, into the process chamber, of a first precursor and a second precursor, respectively. The deposition cycle further comprises a first purge pulse and a second purge pulse for removing, from the process chamber, a portion of the first precursor and a portion of the second precursor, respectively. The process chamber is maintained, during the deposition cycle, at a process temperature in a range from about 400° C. to about 650° C. and at a first pressure being different from a second pressure, during the first deposition pulse and during the second deposition pulse, respectively.

公开(公告)号：US20230230833A1

公开(公告)日：2023-07-20

申请号：US18127201

申请日：2023-03-28

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Steven van Aerde ,  Bert Jongbloed ,  Kelly Houben ,  Werner Knaepen ,  Wilco Verweij

IPC: H01L21/02 ,  H10B43/27

CPC classification number: H01L21/0262 ,  H01L21/02532 ,  H10B43/27

Abstract: A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

公开(公告)号：US11694892B2

公开(公告)日：2023-07-04

申请号：US17370197

申请日：2021-07-08

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Gido van Der Star ,  Toshiya Suzuki

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/455 ,  C23C16/50 ,  H01L21/762

CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/45536 ,  C23C16/50 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/76224

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

公开(公告)号：US20230207309A1

公开(公告)日：2023-06-29

申请号：US18117729

申请日：2023-03-06

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Steven R.A. Van Aerde ,  Suvi Haukka ,  Atsuki Fukazawa ,  Hideaki Fukuda

IPC: H01L21/02 ,  H01J37/32 ,  H01L21/762 ,  C23C16/455 ,  C23C16/04 ,  C23C16/40

CPC classification number: H01L21/0228 ,  H01J37/32009 ,  H01L21/76224 ,  H01L21/02274 ,  H01L21/02178 ,  H01L21/02299 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02219 ,  C23C16/45534 ,  C23C16/45542 ,  C23C16/045 ,  C23C16/402 ,  H01J2237/334 ,  H01J2237/3321

Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a sub saturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

公开(公告)号：US20230140283A1

公开(公告)日：2023-05-04

申请号：US18051803

申请日：2022-11-01

Applicant: ASM IP Holding B.V.

Inventor： Theodorus G.M. Oosterlaken ,  Dieter Pierreux

IPC: H01L21/673 ,  C23C16/458

Abstract: A semiconductor substrate processing apparatus, comprising a processing chamber, a wafer boat and a plurality of wafer supports. The wafer boat is configured to accommodate a plurality of wafers and is receivable in the processing chamber for depositing a layer on each wafer. The wafer boat comprises at least two wafer boat posts, wherein each wafer boat post comprises a plurality of slots. Each wafer support comprises a support area configured to support at least a circumferential edge of a wafer, and a flange circumferentially surrounding the support area. The flange is receivable in and supported by the slots and has a width to create a distance between the circumferential edge of the wafer and the wafer boat posts. The distance is such that the wafer boat posts do substantially not influence a layer thickness of the layer which is deposited on the wafer during processing of the wafer.

公开(公告)号：US11610775B2

公开(公告)日：2023-03-21

申请号：US16318094

申请日：2017-07-14

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Steven R. A. Van Aerde ,  Suvi Haukka ,  Atsuki Fukazawa ,  Hideaki Fukuda

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/455 ,  H01L21/762 ,  C23C16/04 ,  C23C16/40

Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

公开(公告)号：US11532757B2

公开(公告)日：2022-12-20

申请号：US15726959

申请日：2017-10-06

Applicant: ASM IP Holding B.V.

Inventor： Pauline Calka ,  Qi Xie ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L29/792 ,  C23C16/30 ,  H01L27/11582 ,  C23C16/455 ,  H01L27/1157 ,  H01L21/02 ,  C23C16/34 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/66

Abstract: A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.