公开(公告)号：US20050054202A1

公开(公告)日：2005-03-10

申请号：US10655972

申请日：2003-09-04

申请人： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

发明人： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC分类号： H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768

CPC分类号： H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

摘要： A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

摘要翻译： 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US20050045092A1

公开(公告)日：2005-03-03

申请号：US10653852

申请日：2003-09-03

申请人： Chii-Ming Wu ,  Chao-Hsien Peng ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Chao-Hsien Peng ,  Shau-Lin Shue

IPC分类号： C30B25/02 ,  C30B25/14 ,  H01L21/314 ,  H01L21/316 ,  C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： H01L21/0228 ,  C30B25/02 ,  C30B25/14 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645

摘要： An ALD method is described for depositing a composite layer comprised of three to five elements including one or two metals, Si, B and N. A metal containing gas is injected into a process chamber and purged followed by a N source gas and a purge and/or a Si or B source gas and a purge to complete a cycle and form a monolayer. A predetermined number of monolayers each having two or three elements is deposited to provide a composite film with good step coverage and a well controlled composition. The resulting layer is especially useful as a diffusion barrier layer for copper. Alternatively, a three component layer comprised of Hf, Zr, and O may be deposited and serves as a gate dielectric layer in a MOSFET device. The invention is also a thin film comprised of a plurality of monolayers each having two or three elements.

摘要翻译： 描述了一种ALD方法，用于沉积由包括一种或两种金属Si，B和N的三至五个元素组成的复合层。将含金属的气体注入到处理室中，然后吹扫N源气体和吹扫， /或Si或B源气体和吹扫以完成循环并形成单层。 沉积预定数量的具有两个或三个元素的单层，以提供具有良好的步骤覆盖率和良好控制的组合物的复合膜。 所得的层特别适用于铜的扩散阻挡层。 或者，可以沉积由Hf，Zr和O组成的三组分层，并且用作MOSFET器件中的栅介质层。 本发明也是由多个单层组成的薄膜，每个单层具有两个或三个元素。

公开(公告)号：US06759750B2

公开(公告)日：2004-07-06

申请号：US10623910

申请日：2003-07-18

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai

IPC分类号： H01L2348

CPC分类号： H01L23/522 ,  H01L21/76801 ,  H01L21/76807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.

摘要翻译： 一种用于在半导体制造中集成低K材料的方法。 该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。 图案化电介质层以形成柱状开口。 在半导体结构上沉积柱层; 从而用柱层填充柱状开口。 柱层被平坦化以形成嵌入在所述介电层中的柱。 柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。 在一个实施例中，在形成双镶嵌层间接触之前形成柱。 在另一个实施方案中，柱与层间接触同时形成。

公开(公告)号：US06686280B1

公开(公告)日：2004-02-03

申请号：US09989802

申请日：2001-11-20

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

公开(公告)号：US06620725B1

公开(公告)日：2003-09-16

申请号：US09395287

申请日：1999-09-13

申请人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Ying-Ho Chen ,  Tsu Shih ,  Jih-Churng Twu ,  Syun-Ming Jang

IPC分类号： H01L214763

CPC分类号： H01L21/7684 ,  H01L21/3212

摘要： A process for performing CMP in two steps is described. After trenches have been formed and over-filled with copper, in a first embodiment of the invention a hard pad is used initially to remove most of the copper until a point is reached where dishing effects would begin to appear. A soft pad is then substituted and CMP continued until all copper has been removed, except in the trenches. In a second embodiment, CMP is initiated using a pad to which high-pressure is applied and which rotates relatively slowly. As before, this combination is used until the point is reached where dishing effects would begin to appear. Then, relatively low pressure in combination with relatively high rotational speed is used until all copper has been removed, except in the trenches. Both of these embodiments result in trenches which are just-filled with copper, with little or no dishing effects, and with all traces of copper removed everywhere except in the trenches themselves.

摘要翻译： 描述用于在两个步骤中执行CMP的过程。 在沟槽已经形成并且用铜过度填充之后，在本发明的第一实施例中，最初使用硬焊盘去除大部分铜，直到达到一个点，其中凹陷效应将开始出现。 然后取代软焊盘，继续CMP直到除了沟槽中除去所有的铜。 在第二实施例中，使用施加高压并且相对缓慢地旋转的衬垫来启动CMP。 如前所述，使用这种组合，直到达到点，其中凹陷效应将开始出现。 然后，除了沟槽之外，使用相对较低的压力结合相对高的转速直到除去所有的铜。 这两个实施例都导致刚好填充铜的沟槽，几乎没有凹陷效应，并且除了沟槽本身之外，所有痕迹的铜都被去除。

公开(公告)号：US06562725B2

公开(公告)日：2003-05-13

申请号：US09899420

申请日：2001-07-05

申请人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76829 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/7681 ,  H01L21/76834

摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.

摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。 第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。 通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

公开(公告)号：US06531389B1

公开(公告)日：2003-03-11

申请号：US09467130

申请日：1999-12-20

申请人： Shau-Lin Shue ,  Mei-Yun Wang

发明人： Shau-Lin Shue ,  Mei-Yun Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  Y10S438/958

摘要： A method for forming a via through a dielectric layer. There is first provided a substrate. There is then formed over the substrate a patterned conductor layer. There is then formed covering the patterned conductor layer a dielectric layer. There is then formed through the dielectric layer a via to access the patterned conductor layer, where the via is incompletely landed upon the patterned conductor layer. There is then purged the via while employing a vacuum purging method to form a purged via. There is then passivated the purged via and passivated the patterned conductor layer exposed within the purged via while employing a plasma passivation method to form a plasma passivated purged via and a plasma passivated patterned conductor layer. Finally, there is then formed into the plasma passivated purged via a conductor stud layer. Incident to employing the purging of the via to form the purged via and the plasma passivating of the purged via to form the plasma passivated purged via, the conductor stud layer when formed into the plasma passivated purged via is formed with attenuated contact resistance with respect to the plasma passivated patterned conductor layer.

摘要翻译： 一种通过电介质层形成通孔的方法。 首先提供基板。 然后在衬底上形成图案化的导体层。 然后形成覆盖图案化导体层的电介质层。 然后通过电介质层形成通孔以访问图案化的导体层，其中通孔不完全地着落在图案化的导体层上。 然后在使用真空吹扫方法的同时吹扫通孔以形成清洗的通孔。 然后钝化净化的通孔并钝化暴露在清洗过的通孔内的图案化导体层，同时采用等离子体钝化方法形成等离子体钝化清洗的通孔和等离子体钝化的图案化导体层。 最后，然后形成通过导体柱层被钝化的等离子体钝化。 为了采用清洗通孔以形成清洗过的通孔和被清除通孔的等离子体钝化以形成等离子体钝化净化通孔的事件，当形成等离子体钝化净化过的通孔时，导体柱层形成相对于 等离子体钝化图案化导体层。

公开(公告)号：US06297158B1

公开(公告)日：2001-10-02

申请号：US09583402

申请日：2000-05-31

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

摘要： In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

摘要翻译： 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。

公开(公告)号：US06245675B1

公开(公告)日：2001-06-12

申请号：US09489966

申请日：2000-01-24

申请人： Mong-Song Liang ,  Shau-Lin Shue

发明人： Mong-Song Liang ,  Shau-Lin Shue

IPC分类号： H01L214763

CPC分类号： H01L21/76879

摘要： A new method of metallization using a three-dimensional aluminum reservoir to increase the electromigration lifetime of a tungsten plug in the fabrication of integrated circuits is achieved. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. Aluminum lines are formed over the insulating layer. An intermetal dielectric layer is deposited overlying the aluminum lines. Via openings are made through the intermetal dielectric layer to the aluminum lines. Aluminum is selectively deposited into the via openings to form aluminum reservoirs in the bottom of the via openings wherein the aluminum does not completely fill the via openings. Tungsten plugs are formed within the via openings overlying the aluminum reservoirs wherein the aluminum reservoirs provide a source for electrons to replenish electrons lost through electromigration to complete formation of tungsten plug metallization with increased electromigration lifetime in the fabrication of integrated circuits.

摘要翻译： 实现了在集成电路制造中使用三维铝储存器来增加钨插塞的电迁移寿命的新的金属化方法。 提供了覆盖半导体衬底中的半导体器件结构的绝缘层。 在绝缘层上形成铝线。 金属间电介质层沉积在铝线上。 通过开口穿过金属间电介质层到铝线。 选择性地将铝沉积到通孔开口中以在通孔开口的底部形成铝储存器，其中铝不完全填充通孔。 钨插塞形成在覆盖铝储存器的通孔开口中，其中铝储存器提供电子源以补充通过电迁移损失的电子，以在集成电路的制造中增加电迁移寿命来完成钨插塞金属化的形成。

公开(公告)号：US06224737B1

公开(公告)日：2001-05-01

申请号：US09377540

申请日：1999-08-19

申请人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Wen-Jye Tsai ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： C25D502

CPC分类号： H01L21/76877 ,  C25D3/38 ,  C25D5/48 ,  C25D7/123 ,  H01L21/2885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.

摘要翻译： 提供具有形成在其中的沟槽的半导体结构。 半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。 电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。 将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。 由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。 然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。 然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。