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    Multi-chip packaging having non-sticking test structure
    71.
    发明授权
    Multi-chip packaging having non-sticking test structure 失效
    具有不粘试验结构的多芯片封装

    公开(公告)号：US06392425B1

    公开(公告)日：2002-05-21

    申请号：US09475005

    申请日：1999-12-30

    申请人： April Chen ,  Chih-Chin Liao ,  Tzong-Dar Her

    发明人： April Chen ,  Chih-Chin Liao ,  Tzong-Dar Her

    IPC分类号： G01R3102

    CPC分类号： G01R1/0483 ,  H01L2224/48463 ,  H01L2224/85181

    摘要： A multi-chip packaging substrate having a non-sticking test structure consists of a plurality of non-sticking test spots formed in the periphery zone outside the chip-packaging zone of a multi-chip packaging substrate. Each of these non-sticking test spots is electrically connected to an adjacent one of a plurality of chip pads respectively in the chip packaging zone through a plurality of conductive traces while there are no electrical connections connected one another among the chip pads.

    摘要翻译： 具有不粘试验结构的多芯片封装基板由在多芯片封装基板的芯片封装区域外部的外围区域形成的多个不粘附试验点构成。 这些不粘贴的测试点中的每一个都通过多个导电迹线电连接到芯片封装区域中的多个芯片焊盘中的相邻的一个，同时在芯片焊盘之间没有彼此连接的电连接。

    High density three dimensional semiconductor die package
    72.
    发明授权
    High density three dimensional semiconductor die package 有权
    高密度三维半导体芯片封装

    公开(公告)号：US08653653B2

    公开(公告)日：2014-02-18

    申请号：US12648697

    申请日：2009-12-29

    申请人： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

    发明人： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

    IPC分类号： H01L23/34

    CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

    摘要翻译： 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

    Ball grid array package with interdigitated power ring and ground ring
    76.
    发明授权
    Ball grid array package with interdigitated power ring and ground ring 有权
    球形阵列封装，带有交错电源环和接地环

    公开(公告)号：US06449169B1

    公开(公告)日：2002-09-10

    申请号：US09796316

    申请日：2001-02-28

    申请人： Tzong-Da Ho ,  Chih-Chin Liao ,  Chien-Te Chen

    发明人： Tzong-Da Ho ,  Chih-Chin Liao ,  Chien-Te Chen

    IPC分类号： H05K118

    CPC分类号： H01L24/49 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

    摘要： A BGA (Ball Grid Array) package is proposed, which is characterized by the provision of an interdigitated power/ground ring layout scheme. By this layout scheme, the power ring and the ground ring are each formed with a line portion and a plurality of toothed portions; with the toothed portions of the power ring being are interdigitated with the toothed portions of the ground ring. Moreover, the power/ground vias are all connected to the toothed portions of the power ring and the ground ring, thereby leaving the line portions of the power ring and the ground ring unoccupied by the power/ground vias, allowing the routability of power/ground wires to be higher than the prior art. Moreover, solder bask is formed in such a manner as to cover all the toothed portions of the ground ring, so that power wires can be prevented from being short-circuited to the ground ring due to sagging. Further, the toothed portions of the power ring and the ground ring are large in area, whereby two or more power vias or ground vias can be gathered together to increase the overall electrical performance, and whereby the packaged chip can be increased in heat-dissipation efficiency.

    摘要翻译： 提出了一种BGA（球栅阵列）封装，其特征在于提供交叉电源/接地环布局方案。 通过该布置方案，功率环和接地环各自形成有线部分和多个齿形部分; 电源环的齿形部分与接地环的齿形部分交错。 此外，电源/接地通孔都连接到电源环和接地环的齿形部分，从而使电源环和接地环的线路部分不被电源/接地通孔占据，从而允许电力/ 接地线高于现有技术。 此外，焊盘以覆盖接地环的所有齿部的方式形成，从而可以防止电源线由于下垂而与接地环短路。 此外，电源环和接地环的齿形部分面积大，由此可以将两个或更多个电源通孔或接地通孔聚集在一起以增加整体电气性能，从而可以增加封装芯片的散热能力 效率。

    Method for identifying defective elements in array molding of semiconductor packaging
    80.
    发明授权
    Method for identifying defective elements in array molding of semiconductor packaging 有权

    公开(公告)号：US06391666B1

    公开(公告)日：2002-05-21

    申请号：US09475007

    申请日：1999-12-30

    申请人： Ya-Hui Huang ,  Chih-Chin Liao ,  Tzong-Dar Her

    发明人： Ya-Hui Huang ,  Chih-Chin Liao ,  Tzong-Dar Her

    IPC分类号： H01L2166

    摘要： The present invention is a method for identifying defective elements in array molding of semiconductor packaging for mini BGA packaging substrate which comprises a circuit zone and a periphery zone. The method of the present invention is first to form a plurality of package sites disposed in array in the circuit zone, and to form a plurality of marks in a periphery zone. When a defective element is found in the package sites, a symbol is put at the mark or an electronic file is employed to record the location of the defective element, thereby, the defective element in the package sites of the molding array in the circuit zone can be identified.