公开(公告)号：US08653653B2

公开(公告)日：2014-02-18

申请号：US12648697

申请日：2009-12-29

Applicant: Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

Inventor： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  G11C5/02 ,  G11C5/04 ,  G11C5/143 ,  G11C8/12 ,  H01L21/485 ,  H01L23/5382 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06579 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates. By providing each flash memory semiconductor die on a substrate with a unique layout of address traces, each memory die may be selectively addressed by the controller die.

Abstract translation: 公开了一种半导体封装，其包括安装在基板的堆叠和接合层上的多个半导体管芯，例如在带自动焊接工艺中使用的聚酰亚胺带。 带可以具有多个重复图案的迹线和形成在其上的接触垫。 每个迹线包括在衬底的相应顶部和底部表面上的对准的互连焊盘，用于在将图案从基板切割成对准和堆叠之后将一个图案的迹线粘合到另一图案的迹线。 诸如闪速存储器和控制器管芯的半导体管芯安装在衬底上各个图案的迹线上。 为了使控制器裸片独特地寻址堆叠中的特定闪存芯片，支持存储芯片的每个衬底上的一组迹线被用作地址引脚，并相对于其它衬底的迹线的布局以独特的布局冲压。 通过在基板上提供具有唯一的地址迹线布局的每个闪速存储器半导体管芯，每个存储管芯可以被控制器管芯选择性地寻址。

公开(公告)号：US20110316164A1

公开(公告)日：2011-12-29

申请号：US12825617

申请日：2010-06-29

Applicant: Chih-Chin Liao ,  Cheeman Yu

Inventor： Chih-Chin Liao ,  Cheeman Yu

IPC: H01L25/065 ,  H01L21/60 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/50 ,  H01L24/04 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01013 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die.

Abstract translation: 公开了一种由其形成的半导体管芯和半导体封装以及半导体管芯和封装件的制造方法。 半导体管芯包括形成有由凹陷之间的突起限定的多个波纹的边缘。 接合焊盘可以形成在突起上。 以这种方式形成的半导体管芯可以以交错对堆叠在半导体封装中，使得下模具的突起上的管芯接合焊盘定位在上模的凹部中。

公开(公告)号：US20100055836A1

公开(公告)日：2010-03-04

申请号：US12614998

申请日：2009-11-09

Applicant: Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

Inventor： Cheeman Yu ,  Chih-Chin Liao ,  Hem Takiar

IPC: H01L21/56

CPC classification number: H01L24/49 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract translation: 公开了一种包括多个堆叠的半导体封装的电子部件。 第一个这样的实施例包括用于电耦合堆叠的半导体封装的内部连接器。 第二个这样的实施例包括用于电耦合堆叠的半导体封装的外部连接器。

公开(公告)号：US08502375B2

公开(公告)日：2013-08-06

申请号：US12825617

申请日：2010-06-29

Applicant: Chih-Chin Liao ,  Cheeman Yu

Inventor： Chih-Chin Liao ,  Cheeman Yu

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/50 ,  H01L24/04 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01013 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor die and semiconductor package formed therefrom, and methods of fabricating the semiconductor die and package, are disclosed. The semiconductor die includes an edge formed with a plurality of corrugations defined by protrusions between recesses. Bond pads may be formed on the protrusions. The semiconductor die formed in this manner may be stacked in the semiconductor package in staggered pairs so that the die bond pads on the protrusions of a lower die are positioned in the recesses of the upper die.

Abstract translation: 公开了一种由其形成的半导体管芯和半导体封装以及半导体管芯和封装件的制造方法。 半导体管芯包括形成有由凹陷之间的突起限定的多个波纹的边缘。 接合焊盘可以形成在突起上。 以这种方式形成的半导体管芯可以以交错对堆叠在半导体封装中，使得下模具的突起上的管芯接合焊盘位于上模的凹部中。

公开(公告)号：US20130015589A1

公开(公告)日：2013-01-17

申请号：US13265662

申请日：2011-07-14

Applicant: Chih-Chin Liao ,  Chin-Tien Chiu ,  Cheeman Yu ,  Suresh Kumar Upadhyayula ,  Wen Cheng Li ,  Zhong Lu

Inventor： Chih-Chin Liao ,  Chin-Tien Chiu ,  Cheeman Yu ,  Suresh Kumar Upadhyayula ,  Wen Cheng Li ,  Zhong Lu

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A multi-die semiconductor device is disclosed. The device may include one or more first-sized die on a substrate and one or more second-sized die affixed over the one or more first-sized die. The second-sized die may have a larger footprint than the first-sized die. An internal molding compound may be provided on the substrate having a footprint the same size as the second-sized die. The second-sized die may be supported on the internal molding compound. Thereafter, the first and second-sized die and the internal molding compound may be encapsulated in an external molding compound.

Abstract translation: 公开了一种多芯片半导体器件。 该装置可以包括在基底上的一个或多个第一尺寸的模具和一个或多个第二尺寸的模具，该模具固定在一个或多个第一尺寸模具上。 第二尺寸的模具可以具有比第一尺寸的模具更大的占地面积。 可以在衬底上设置内部模制化合物，其尺寸与第二尺寸模具相同。 第二尺寸的模具可以支撑在内部模塑料上。 此后，第一和第二尺寸模具和内部模塑料可以封装在外部模塑料中。

公开(公告)号：US09209159B2

公开(公告)日：2015-12-08

申请号：US13411308

申请日：2012-03-02

Applicant: Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/3205 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

公开(公告)号：US08415808B2

公开(公告)日：2013-04-09

申请号：US12844959

申请日：2010-07-28

Applicant: Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

Inventor： Chih-Chin Liao ,  Cheeman Yu ,  Ya Huei Lee

IPC: H01L23/48

CPC classification number: H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package.

Abstract translation: 公开了一种半导体管芯封装。 半导体封装的示例包括散布有第二组半导体管芯的第一组半导体管芯。 来自第一组和第二组的模具沿着第一轴线彼此偏移并且沿着与第一轴线正交的第二轴线相对于彼此交错。 半导体封装的第二示例包括不规则形状的边缘和从封装中的最低半导体管芯上方的半导体管芯到基板的引线接合。

公开(公告)号：US08217522B2

公开(公告)日：2012-07-10

申请号：US12819840

申请日：2010-06-21

Applicant: Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheeman Yu ,  Hem Takiar

Inventor： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheeman Yu ,  Hem Takiar

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract translation: 公开了具有共同的电连接器和接触焊盘区域的印刷电路板。 迹线和/或通孔所在接触焊盘区域可被蚀刻掉，以确保迹线，通孔和接触焊盘之间的电气隔离。

公开(公告)号：US20120164828A1

公开(公告)日：2012-06-28

申请号：US13411308

申请日：2012-03-02

Applicant: Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

Inventor： Hem Takiar ,  Cheeman Yu ,  Ken Jian Ming Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC: H01L21/3205

CPC classification number: H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract translation: 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20100252315A1

公开(公告)日：2010-10-07

申请号：US12819840

申请日：2010-06-21

Applicant: Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheeman Yu ,  Hem Takiar

Inventor： Chih-Chin Liao ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Ken Jian Ming Wang ,  Cheeman Yu ,  Hem Takiar

IPC: H05K1/18

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4038 ,  H05K3/429 ,  H05K2201/0195 ,  H05K2201/0338 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract translation: 公开了具有共同的电连接器和接触焊盘区域的印刷电路板。 迹线和/或通孔所在接触焊盘区域可被蚀刻掉，以确保迹线，通孔和接触焊盘之间的电气隔离。