公开(公告)号：US20100270683A1

公开(公告)日：2010-10-28

申请号：US12662335

申请日：2010-04-12

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/76834 ,  H01L21/76885 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect.

摘要翻译： 在第一绝缘层中提供互连，并且互连的上表面高于第一绝缘层的上表面。 在互连和第一绝缘层之间设置气隙。 在第一绝缘层，气隙和互连件之上形成蚀刻阻挡膜。 在蚀刻停止膜上形成第二绝缘层。 通孔设置在第二绝缘层中并连接到互连。 设置在气隙上的蚀刻阻挡膜的一部分比设置在互连上的另一部分厚。

公开(公告)号：US07745937B2

公开(公告)日：2010-06-29

申请号：US11355003

申请日：2006-02-16

申请人： Tatsuya Usami ,  Koichi Ohto ,  Toshiyuki Takewaki

发明人： Tatsuya Usami ,  Koichi Ohto ,  Toshiyuki Takewaki

IPC分类号： H01L23/48

CPC分类号： H01L21/76867 ,  H01L21/02203 ,  H01L21/02329 ,  H01L21/3143 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76849 ,  H01L21/76886

摘要： A first gas including a silicon-containing compound is introduced into a vacuum chamber, to expose a semiconductor substrate placed in the chamber to the first gas atmosphere (silicon processing step). Then the pressure inside the vacuum chamber is reduced to a level lower than the pressure at the time of starting the silicon processing step (depressurizing step). Thereafter, a second gas including a nitrogen-containing compound is introduced into the vacuum chamber, and the semiconductor substrate is irradiated with the second gas plasma (nitrogen plasma step).

摘要翻译： 将包含含硅化合物的第一气体引入真空室中，以将放置在室内的半导体衬底暴露于第一气体气氛（硅处理步骤）。 然后将真空室内的压力降低到低于开始硅处理步骤（减压步骤）时的压力的水平。 此后，将包含含氮化合物的第二气体引入真空室中，并用第二气体等离子体（氮等离子体步骤）照射半导体衬底。

公开(公告)号：US20080070400A1

公开(公告)日：2008-03-20

申请号：US11892923

申请日：2007-08-28

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/283 ,  H01L21/318

CPC分类号： H01L21/0337 ,  H01L21/3185 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599

摘要： When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even when the film forming temperature is made not more than an allowable temperature limit of an adhesive to adhere a support (for example, approximately 100° C. or less, which is an allowable temperature limit when the adhesive is an ultraviolet curing resin), a high-quality film without exfoliation in a CMP step of the following step and with less leakage can be formed. This high-quality film is, if being prescribed by a refractive index, a film whose refractive index with respect to a wavelength of 633 nm is approximately 1.8 through 1.9.

摘要翻译： 当形成氮化硅膜以保护和绝缘其上已经研磨或抛光硅衬底的表面时，通过使用含有SiH 4 N 2 N 2的混合气体， 和NH 3作为反应气体，通过单频平行板等离子体CVD法形成膜。 因此，即使当成膜温度不大于粘合剂的粘合剂的允许温度极限时（例如约100℃或更低，这是当粘合剂是紫外线固化树脂时的允许温度极限） ），可以形成在后续步骤的CMP步骤中没有剥离并且具有较少泄漏的高质量膜。 如果由折射率规定，则该高品质膜的折射率相对于633nm的折射率为1.8〜1.9左右。

公开(公告)号：US07291911B2

公开(公告)日：2007-11-06

申请号：US11047576

申请日：2005-02-02

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L23/48

CPC分类号： H01L21/0337 ,  H01L21/3185 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599

摘要： When forming a silicon nitride film to protect and insulate a surface on which a silicon substrate has been ground or polishing, by use of a mixed gas containing SiH4, N2, and NH3 as a reaction gas, a film is formed by a single-frequency parallel-plate plasma CVD method. Thereby, even when the film forming temperature is made not more than an allowable temperature limit of an adhesive to adhere a support (for example, approximately 100° C. or less, which is an allowable temperature limit when the adhesive is an ultraviolet curing resin), a high-quality film without exfoliation in a CMP step of the following step and with less leakage can be formed. This high-quality film is, if being prescribed by a refractive index, a film whose refractive index with respect to a wavelength of 633 nm is approximately 1.8 through 1.9.

摘要翻译： 当形成氮化硅膜以保护和绝缘其上已经研磨或抛光硅衬底的表面时，通过使用含有SiH 4 N 2 N 2的混合气体， 和NH 3作为反应气体，通过单频平行板等离子体CVD法形成膜。 因此，即使当成膜温度不大于粘合剂的粘合剂的允许温度极限时（例如约100℃或更低，这是当粘合剂是紫外线固化树脂时的允许温度极限） ），可以形成在后续步骤的CMP步骤中没有剥离并且具有较少泄漏的高质量膜。 如果由折射率规定，则该高品质膜的折射率相对于633nm的折射率为1.8〜1.9左右。

公开(公告)号：US07230337B2

公开(公告)日：2007-06-12

申请号：US10760554

申请日：2004-01-21

申请人： Tatsuya Usami ,  Takashi Ishigami ,  Tetsuya Kurokawa ,  Noriaki Oda

发明人： Tatsuya Usami ,  Takashi Ishigami ,  Tetsuya Kurokawa ,  Noriaki Oda

IPC分类号： H01L23/48 ,  H01L23/29 ,  H01L23/28 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L23/53295 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention reduces the effective dielectric constant of the interlayer insulating film while inhibiting the decrease of the reliability of the semiconductor device, which otherwise is caused by a moisture absorption. A copper interconnect comprising a Cu film 209 is formed in multilayer films comprising a L-Ox™ film 203 and a SiO2 film 204. Since the L-Ox™ film 203 comprises ladder-shaped siloxane hydride structure, the film thickness and the film characteristics are stable, and thus changes in the film quality is scarcely occurred during the manufacturing process.

摘要翻译： 本发明降低了层间绝缘膜的有效介电常数，同时抑制了由吸湿引起的半导体器件的可靠性的降低。 包括Cu膜209的铜互连形成在包括L-Ox TM膜203和SiO 2膜204的多层膜中。 由于L-Ox TM膜203包括梯形硅氢化合物结构，所以膜厚度和膜特性是稳定的，因此在制造过程中几乎不发生膜质量的变化。

公开(公告)号：US07229910B2

公开(公告)日：2007-06-12

申请号：US10135393

申请日：2002-05-01

申请人： Tatsuya Usami

发明人： Tatsuya Usami

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： The object of the present invention is to improve the interfacial adhesion between the film with low dielectric constant and protective film, without damaging the excellent dielectric, flatness and gap-filling characteristics of the organic material of low dielectric constant, and for that purpose there is provided a wiring structure with the copper film embedded in the insulation film of the wiring layer, wherein the insulation film of the wiring layer is of a multi-layered structure with the laminated methyl silisesquioxane (MSQ) film, methylated hydrogen silisesquioxane (MHSQ) film and silicon oxide film.

摘要翻译： 本发明的目的是提高具有低介电常数的膜和保护膜之间的界面粘合性，而不损害低介电常数有机材料的优异的电介质，平坦度和间隙填充特性，并且为此目的 提供了布线结构，其中铜膜嵌入在布线层的绝缘膜中，其中布线层的绝缘膜具有层叠的甲基silisquioxane（MSQ）膜，甲基化氢硅烷倍半硅氧烷（MHSQ）膜的多层结构 和氧化硅膜。

公开(公告)号：US20070117405A1

公开(公告)日：2007-05-24

申请号：US11655261

申请日：2007-01-19

申请人： Yoichi Sasaki ,  Koichi Ohto ,  Noboru Morita ,  Tatsuya Usami ,  Hidenobu Miyamoto

发明人： Yoichi Sasaki ,  Koichi Ohto ,  Noboru Morita ,  Tatsuya Usami ,  Hidenobu Miyamoto

IPC分类号： H01L21/31

CPC分类号： H01L21/76835 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76832

摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.

摘要翻译： 半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210， SUB>膜212和形成在其上的SiCN膜214。 第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。 第二SiOC膜210的碳含量被调整为大于第一SiOC膜204的碳含量。 这使得可以在保持绝缘中间层的低介电常数的同时提高绝缘中间层与其它绝缘层的粘附性。

公开(公告)号：US20070108620A1

公开(公告)日：2007-05-17

申请号：US11647187

申请日：2006-12-29

申请人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

发明人： Koichi Ohto ,  Toshiyuki Takewaki ,  Tatsuya Usami ,  Nobuyuki Yamanishi

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/022 ,  H01L21/02074 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3124 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer.

摘要翻译： 在半导体器件中，在绝缘底层上形成具有凹槽的绝缘中间层。 不含金属硅化物的硅扩散金属层埋入槽内。 在硅扩散金属层和绝缘中间层上形成金属扩散阻挡层。

公开(公告)号：US07217654B2

公开(公告)日：2007-05-15

申请号：US10969429

申请日：2004-10-21

申请人： Seiji Nagahara ,  Kazutoshi Shiba ,  Nobuaki Hamanaka ,  Tatsuya Usami ,  Takashi Yokoyama

发明人： Seiji Nagahara ,  Kazutoshi Shiba ,  Nobuaki Hamanaka ,  Tatsuya Usami ,  Takashi Yokoyama

IPC分类号： H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76831

摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).

摘要翻译： 一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。 在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是 进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

公开(公告)号：US20070096331A1

公开(公告)日：2007-05-03

申请号：US11640349

申请日：2006-12-18

申请人： Seiji Nagahara ,  Kazutoshi Shiba ,  Nobuaki Hamanaka ,  Tatsuya Usami ,  Takashi Yokoyama

发明人： Seiji Nagahara ,  Kazutoshi Shiba ,  Nobuaki Hamanaka ,  Tatsuya Usami ,  Takashi Yokoyama

IPC分类号： H01L23/48

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76831

摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.

摘要翻译： 一种制造具有镶嵌结构的半导体器件的方法包括在基板上形成第一层间绝缘膜和由低介电常数膜形成的第二层间绝缘膜的工艺，通过使用形成在第一层上绝缘膜上的第一抗蚀剂图案形成通孔 第二层间绝缘膜，使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案。 在第二抗反射涂层涂布第二抗蚀剂图案之下的湿处理之后，涂覆第二抗蚀图案，进行退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一种以除去胺 抑制在曝光时在抗蚀剂中发生的酸的催化反应的成分，从而防止第二抗蚀剂图案的分辨率的劣化。