公开(公告)号：US20250112181A1

公开(公告)日：2025-04-03

申请号：US18374522

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Feras Eid ,  Yi Shi ,  Kimin Jun ,  Adel Elsherbini ,  Thomas Sounart ,  Wenhao Li ,  Xavier Brun

IPC: H01L23/00 ,  H01L23/367 ,  H01L25/065

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.

公开(公告)号：US20250112173A1

公开(公告)日：2025-04-03

申请号：US18374577

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Thomas Sounart ,  Yi Shi ,  Wenhao Li

IPC: H01L23/00 ,  H01L23/31

Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.

公开(公告)号：US20250112077A1

公开(公告)日：2025-04-03

申请号：US18478391

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Feras Eid ,  Andrey Vyatskikh ,  Adel Elsherbini ,  Brandon M. Rawlings ,  Tushar Kanti Talukdar ,  Thomas L. Sounart ,  Kimin Jun ,  Johanna Swan ,  Grant M. Kloster ,  Carlos Bedoya Arroyave

IPC: H01L21/683 ,  H01L23/00 ,  H01L23/538

Abstract: An embodiment discloses an electronic device comprising an integrated circuit (IC) die, a stub extending from the IC die; and a mesa structure under the IC die, wherein the IC die and the stub are bonded to the mesa structure.

公开(公告)号：US12199018B2

公开(公告)日：2025-01-14

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H05K1/11

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US20250006678A1

公开(公告)日：2025-01-02

申请号：US18345437

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Harini Kilambi ,  Kimin Jun ,  Adel A. Elsherbini ,  John Edward Zeug Matthiesen ,  Trianggono Widodo ,  Adita Das ,  Mohit Bhatia ,  Dimitrios Antartis ,  Bhaskar Jyoti Krishnatreya ,  Rajesh Surapaneni ,  Xavier Francois Brun

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.

公开(公告)号：US20240063132A1

公开(公告)日：2024-02-22

申请号：US17820993

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Gerald S. Pasdast ,  Johanna M. Swan ,  Henning Braunisch ,  Kimin Jun ,  Jiraporn Seangatith ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Sathya Narasimman Tiagaraj

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5383 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.

公开(公告)号：US20240063091A1

公开(公告)日：2024-02-22

申请号：US17891735

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Scot Kellar ,  Yoshihiro Tomita ,  Rajiv Mongia ,  Kimin Jun ,  Shawna Liff ,  Wenhao Li ,  Johanna Swan ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Haris Khan Niazi ,  Jiraporn Seangatith ,  Thomas Sounart

IPC: H01L23/473 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L23/373

CPC classification number: H01L23/473 ,  H01L24/08 ,  H01L25/0652 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3677 ,  H01L23/3675 ,  H01L23/3732 ,  H01L23/3738 ,  H01L2924/3511 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/182 ,  H01L2924/186

Abstract: Microelectronic devices, assemblies, and systems include a multichip composite device having one or more chiplets bonded to a base die and an inorganic dielectric material adjacent the chiplets and over the base die. The multichip composite device is coupled to a structural member that is made of or includes a heat conducting material, or has integrated fluidic cooling channels to conduct heat from the chiplets and the base die.

公开(公告)号：US20240063072A1

公开(公告)日：2024-02-22

申请号：US17891530

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Kimin Jun ,  Veronica Strong ,  Aleksandar Aleksov ,  Jiraporn Seangatith ,  Mohammad Enamul Kabir ,  Johanna Swan ,  Tushar Talukdar ,  Omkar Karhade

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/29

CPC classification number: H01L23/3135 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/49816 ,  H01L23/49838 ,  H01L21/568 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/291 ,  H01L24/08

Abstract: Composite integrated circuit (IC) device processing, including selective removal of inorganic dielectric material. Inorganic dielectric material may be deposited, modified with laser exposure, and selectively removed. Laser exposure parameters may be adjusted using surface topography measurements. Inorganic dielectric material removal may reduce surface topography. Vias and trenches of varying size, shape, and depth may be concurrently formed without an etch-stop layer. A composite IC device may include an IC die, a conductive via, and a conductive line adjacent a compositionally homogenous inorganic dielectric material.

公开(公告)号：US11869894B2

公开(公告)日：2024-01-09

申请号：US17864264

申请日：2022-07-13

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Anh Phan ,  Patrick Morrow ,  Willy Rachmady ,  Gilbert Dewey ,  Jessica M. Torres ,  Kimin Jun ,  Tristan A. Tronic ,  Christopher J. Jezewski ,  Hui Jae Yoo ,  Robert S. Chau ,  Chi-Hwa Tsang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/285 ,  H01L21/84 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/28568 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785 ,  H10B61/22 ,  H10B63/30

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

公开(公告)号：US20230411356A1

公开(公告)日：2023-12-21

申请号：US18239549

申请日：2023-08-29

Applicant: Intel Corporation

Inventor： Anup Pancholi ,  Kimin Jun

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L21/6835 ,  H01L24/73 ,  H01L24/92 ,  H01L2225/06586 ,  H01L2221/68372 ,  H01L2224/73209 ,  H01L2224/92133 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L25/50

Abstract: An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.