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    Methods of Manufacturing Embedded Bipolar Switching Resistive Memory
    72.
    发明申请
    Methods of Manufacturing Embedded Bipolar Switching Resistive Memory 审中-公开
    嵌入式双极开关电阻式存储器的制造方法

    公开(公告)号：US20150262663A1

    公开(公告)日：2015-09-17

    申请号：US14728448

    申请日：2015-06-02

    Applicant: Intermolecular, Inc.

    Inventor： Mankoo Lee ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: G11C13/00 ,  H01L29/78 ,  H01L29/868 ,  H01L45/00 ,  H01L27/24

    CPC classification number: G11C13/0033 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/785 ,  H01L29/868 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.

    Abstract translation: 非线性电流响应电路可用于嵌入式电阻式存储单元，以降低功耗，同时提高存储器阵列的可靠性。 非线性电流响应电路可以包括两个背靠背泄漏的PIN二极管，两个并联的反向PIN二极管，两个背靠背的齐纳二极型金属氧化物二极管或者二极管开关元件，以及用于待机功率降低的限流电阻 低电压区域。 此外，所提出的基于1T2D1R方案的嵌入式ReRAM实现方法可以集成到先进的FEOL工艺技术中，包括用于实现高度紧凑的单元密度的立柱晶体管和/或3D鳍状场效应晶体管（FinFET）。

    Systems and Methods for Parallel Combinatorial Vapor Deposition Processing
    73.
    发明申请
    Systems and Methods for Parallel Combinatorial Vapor Deposition Processing 审中-公开
    并联组合气相沉积处理系统与方法

    公开(公告)号：US20150184287A1

    公开(公告)日：2015-07-02

    申请号：US14140874

    申请日：2013-12-26

    Applicant: Intermolecular, Inc.

    Inventor： James Tsung ,  Tony P. Chiang ,  Chien-Lan Hsueh

    IPC: C23C16/44 ,  C23C16/455 ,  C23C16/04

    CPC classification number: C23C16/45561 ,  B01J2219/00394 ,  B01J2219/00412 ,  B01J2219/0043 ,  B01J2219/00443 ,  C23C16/04 ,  C40B60/14

    Abstract: Embodiments described herein provide systems and methods for performing vapor deposition processes on substrates. A housing defining a processing chamber is provided. A substrate support is positioned within the processing chamber and configured to support a substrate. A fluid supply system including a plurality precursor sources is included. A fluid conduit assembly is coupled to the fluid supply system and configurable to selectively expose a first site-isolated region defined on the substrate to the respective precursors of a first and a second of the plurality of precursor sources and selectively expose a second site-isolated region defined on the substrate to the respective precursors of a third and a fourth of the plurality of precursor sources.

    Abstract translation: 本文描述的实施例提供了用于在衬底上进行气相沉积工艺的系统和方法。 提供了限定处理室的壳体。 衬底支撑件定位在处理室内并且构造成支撑衬底。 包括包括多个前体源的流体供应系统。 流体导管组件联接到流体供应系统并且可配置为选择性地将限定在衬底上的第一位置隔离区域暴露于多个前体源中的第一和第二前体源的相应前体，并选择性地暴露第二位点隔离 在所述衬底上限定到所述多个前体源中的第三和第四前体的各个前体的区域。

    Nonvolatile Memory Device Having a Current Limiting Element
    75.
    发明申请
    Nonvolatile Memory Device Having a Current Limiting Element 审中-公开
    具有限流元件的非易失性存储器件

    公开(公告)号：US20150162530A1

    公开(公告)日：2015-06-11

    申请号：US14625867

    申请日：2015-02-19

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1616

    Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

    Abstract translation: 本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。 在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。 所形成的限流层或电阻层的电性能被配置为在逻辑状态编程步骤（即“设定”和“复位”步骤）期间通过添加固定的串联电阻来降低通过可变电阻层的电流 在形成在非易失性存储器件中的电阻式开关存储元件中。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

    Nonvolatile resistive memory element with an oxygen-gettering layer
    76.
    发明申请
    Nonvolatile resistive memory element with an oxygen-gettering layer 审中-公开
    具有吸氧层的非易失性电阻记忆元件

    公开(公告)号：US20150155485A1

    公开(公告)日：2015-06-04

    申请号：US14618138

    申请日：2015-02-10

    Applicant: Intermolecular Inc.

    Inventor： Tony P. Chiang ,  Dipankar Pramanik ,  Milind Weling

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  G11C13/0002 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/145 ,  H01L45/146

    Abstract: A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO2 interfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

    Abstract translation: 非易失性电阻性存储元件包括吸氧层。 吸氧层形成为电极堆叠的一部分，并且在吸电氧中比电极堆叠的其它层更热力学上更有利。 氧吸收层的氧化物的吉布斯自由能（＆Dgr; fG°）比形成电极堆叠的相邻层的氧化物的吉布斯自由能更少（即更负）。 吸氧层与存在于电极堆叠的相邻层中的氧气反应，从而防止这种氧扩散到附近的硅层中，从而不期望地增加存储元件中的SiO 2界面层厚度，并且可以选择以减少这种厚度 后续处理。

    Reduction of forming voltage in semiconductor devices
    77.
    发明申请
    Reduction of forming voltage in semiconductor devices 审中-公开
    降低半导体器件中的形成电压

    公开(公告)号：US20150137064A1

    公开(公告)日：2015-05-21

    申请号：US14595421

    申请日：2015-01-13

    Applicant: Intermolecular Inc.

    Inventor： Pragati Kumar ,  Tony P. Chiang ,  Prashant B. Phatak ,  Yun Wang

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

    Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

    Abstract translation: 本公开提供了一种非易失性存储器件及相关的制造和操作方法。 该装置可以包括一个或多个电阻随机存取存储器（ReRAM）方法来为存储器装置提供更可预测的操作。 特别地，可以通过使用阻挡层，反极性形成电压脉冲，从下功函电极注入电子的形成电压脉冲或还原环境中的退火来降低特定设计所需的形成电压 。 可以根据期望的应用和结果应用这些技术中的一种或多种。

    Resistive-switching nonvolatile memory elements
    78.
    发明授权
    Resistive-switching nonvolatile memory elements 有权
    电阻式开关非易失性存储元件

    公开(公告)号：US09030862B2

    公开(公告)日：2015-05-12

    申请号：US14488494

    申请日：2014-09-17

    Applicant: Intermolecular Inc.

    Inventor： Pragati Kumar ,  Sean Barstow ,  Tony P. Chiang ,  Sandra G Malhotra

    IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24 ,  H01L29/861

    CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/165

    Abstract: Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.

    Abstract translation: 包括电阻开关金属氧化物的非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。

    Amorphous IGZO Devices and Methods for Forming the Same
    80.
    发明申请
    Amorphous IGZO Devices and Methods for Forming the Same 审中-公开
    非晶IGZO器件及其形成方法

    公开(公告)号：US20150079727A1

    公开(公告)日：2015-03-19

    申请号：US14029713

    申请日：2013-09-17

    Applicant: Intermolecular, Inc.

    Inventor： Mankoo Lee ,  Charlene Chen ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L29/66

    CPC classification number: H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78693

    Abstract: Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers.

    Abstract translation: 本文描述的实施例提供了诸如非晶IGZO薄膜晶体管的铟镓镓氧化物器件的改进以及用于形成这种器件的方法。 可以使用相对薄的a-IGZO通道。 可以向前侧a-IGZO界面提供等离子体处理化学前体钝化。 高k电介质材料可用于背面a-IGZO界面的蚀刻停止层。 在栅介质层沉积之前，可以在栅电极上方形成阻挡层。 通常在源极和漏极区域之前形成的常规蚀刻停止层可以由在源极和漏极区域之间形成并且可以包括多个子层形成的预钝化层来代替。

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