公开(公告)号：US20250079398A1

公开(公告)日：2025-03-06

申请号：US18460817

申请日：2023-09-05

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including conductive traces that are parallel to the first and second surfaces and exposed at the third surface; a second IC die having a fourth surface and including voltage regulator circuitry; and a third IC die having a fifth surface, wherein the third surface of the first IC die is electrically coupled to the fifth surface of the third IC die by first interconnects, the fourth surface of the second IC die is electrically coupled to the fifth surface of the third IC die by second interconnects, and the first IC die is electrically coupled to the second IC die by conductive pathways in the third IC die.

公开(公告)号：US20250079392A1

公开(公告)日：2025-03-06

申请号：US18458621

申请日：2023-08-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohammad Enamul Kabir ,  Debendra Mallik

IPC: H01L23/00 ,  H01L25/065

Abstract: Hybrid bonding interconnect (HBI) architectures for scalability. Embodiments implement a bonding layer on a semiconductor die that includes a thick oxide layer overlaid with a thin layer of a hermetic material including silicon and at least one of carbon and nitrogen. The conductive bonds of the semiconductor die are placed in the thick oxide layer and exposed at the surface of the hermetic material. Some embodiments implement a non-bonding moisture seal ring (MSR) structure.

公开(公告)号：US20250006652A1

公开(公告)日：2025-01-02

申请号：US18346098

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Francisco Maya ,  Bhaskar Jyoti Krishnatreya ,  Tan Nguyen ,  Siyan Dong ,  Alveera Gill ,  Keith E. Zawadzki

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus comprising a first integrated circuit device, the first integrated circuit device comprising a first layer with an area comprising metallization and metal-free slits; and a fiducial in a second layer above the first layer, the fiducial formed over the area comprising the metallization and metal-free slits.

公开(公告)号：US12183596B2

公开(公告)日：2024-12-31

申请号：US18226129

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20240272388A1

公开(公告)日：2024-08-15

申请号：US18168927

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande

IPC: G02B6/42

CPC classification number: G02B6/4278 ,  G02B6/4202 ,  G02B6/4243

Abstract: An architecture for v-groove fiber attach for a photonic integrated circuit (PIC). The architecture is characterized by a PIC with a thickness of less than 100 microns. A carrier layer is attached to the non-active surface of the PIC and v-grooves are etched into the active surface of the PIC wafer. The carrier layer functions as an etch stop during the etching of the v-grooves, thereby becoming a floor for the v-grooves and enabling the v-grooves to extend to a depth equal to the thickness of the PIC. The carrier layer can be a glass layer. The carrier layer can also be an electronic integrated circuit (EIC).

公开(公告)号：US20230420432A1

公开(公告)日：2023-12-28

申请号：US17846173

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  G02B6/42

CPC classification number: H01L25/167 ,  H01L24/08 ,  H01L23/3107 ,  H01L24/80 ,  H01L24/94 ,  G02B6/4298 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

公开(公告)号：US20230420411A1

公开(公告)日：2023-12-28

申请号：US17846153

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L25/18 ,  H01L24/06 ,  H01L25/50 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05567 ,  H01L2224/06102 ,  H01L2224/06183 ,  H01L2224/08146 ,  H01L2224/08137 ,  H01L2224/0557 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/80006

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

公开(公告)号：US20230341622A1

公开(公告)日：2023-10-26

申请号：US17725090

申请日：2022-04-20

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Omkar G. Karhade ,  Kaveh Hosseini ,  Tim T. Hoang ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/42

CPC classification number: G02B6/1225 ,  G02B6/428 ,  G02B6/4266 ,  G02B2006/12061

Abstract: Covered cavity structure for Photonic integrated circuits (PICs) that include a micro-ring resonator (MRR) with a heater. Air cavities are etched or otherwise thinned into an overlaying oxide layer, a buried oxide layer, or an underlying silicon layer. Variations in size, shape, and location of the covered air cavity associated with an MRR provide customizable options for thermal management. A thin film across an upper surface covers the air cavity, providing a barrier to underfill in the air cavity and preventing interference of underfill with performance of silicon waveguides. When arrayed into a plurality of MRRs, the thin film can cover the plurality of MRRs.

公开(公告)号：US11764080B2

公开(公告)日：2023-09-19

申请号：US17715923

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/562 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20230092821A1

公开(公告)日：2023-03-23

申请号：US17482213

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Srinivas V. Pietambaram ,  Bharat Prasad Penmecha ,  Mitul Modi

IPC: G02B6/42 ,  G02B6/38

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC is embedded in the insulating material with an active surface facing up; a conductive pillar in the first layer; an integrated circuit (IC) in a second layer on the first layer, wherein the second layer includes the insulating material and the IC is embedded in the insulating material, and wherein the IC is electrically coupled to the active surface of the PIC and the conductive pillar; an optical component optically coupled to the active surface of the PIC; and a hollow channel surrounding the optical component, the hollow channel extending from the active surface of the PIC through the insulating material in the second layer.