公开(公告)号：US12224309B2

公开(公告)日：2025-02-11

申请号：US17116315

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Kaan Oguz ,  I-Cheng Tung ,  Uygar E. Avci ,  Matthew V. Metz ,  Ashish Verma Penumatcha ,  Ian A. Young ,  Arnab Sen Gupta

IPC: H01L23/522 ,  H01L49/02

Abstract: Disclosed herein are capacitors including built-in electric fields, as well as related devices and assemblies. In some embodiments, a capacitor may include a top electrode region, a bottom electrode region, and a dielectric region between and in contact with the top electrode region and the bottom electrode region, wherein the dielectric region includes a perovskite material, and the top electrode region has a different material structure than the bottom electrode region.

公开(公告)号：US12125895B2

公开(公告)日：2024-10-22

申请号：US16915600

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L29/66439 ,  H01L21/02568 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78696 ,  H10B63/30 ,  H10B63/34 ,  H10N70/253

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：US12100731B2

公开(公告)日：2024-09-24

申请号：US16914161

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  I-Cheng Tung ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Matthew Metz ,  Uygar Avci

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L28/65 ,  H01L27/0629 ,  H01L28/55

Abstract: A capacitor device, such as a metal insulator metal (MIM) capacitor includes a seed layer including tantalum, a first electrode on the seed layer, where the first electrode includes at least one of ruthenium or iridium and an insulator layer on the seed layer, where the insulator layer includes oxygen and one or more of Sr, Ba or Ti. In an exemplary embodiment, the insulator layer is a crystallized layer having a substantially smooth surface. A crystallized insulator layer having a substantially smooth surface facilitates low electrical leakage in the MIM capacitor. The capacitor device further includes a second electrode layer on the insulator layer, where the second electrode layer includes a second metal or a second metal alloy.

公开(公告)号：US20240147867A1

公开(公告)日：2024-05-02

申请号：US17978145

申请日：2022-10-31

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Dominique A. Adams ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Kaan Oguz ,  John J. Plombon ,  Ian Alexander Young

IPC: H10N50/10 ,  G11C11/16 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/85

Abstract: Magnetoelectric magnetic tunnel junction (MEMTJ) logic devices comprise a magnetoelectric switching capacitor coupled to a pair of magnetic tunnel junctions (MTJs) by a conductive layer. The logic state of the MEMTJ is represented by the magnetization orientation of the ferromagnetic layer of the magnetoelectric capacitor, which can be switched through the application of an appropriate input voltage to the MEMTJ. The magnetization orientation of the magnetoelectric capacitor ferromagnetic layer is read out by the MTJs. The conductive layer is positioned between the capacitor and the MTJs. The MTJ ferromagnetic free layers are exchange coupled to the ferromagnetic layer of the magnetoelectric capacitor. The potential of an MTJ free layer is based on a supply voltage applied to the reference layer of the MTJ. The MTJ reference layers have a magnetization orientation that is parallel or antiparallel to the magnetization orientations of the ferromagnetic layer of the magnetoelectric capacitor.

公开(公告)号：US20240112731A1

公开(公告)日：2024-04-04

申请号：US17957957

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sou-Chi Chang ,  Chia-Ching Lin ,  Saima Siddiqui ,  Sarah Atanasov ,  Bernal Granados Alpizar ,  Uygar Avci

IPC: G11C13/00 ,  G11C11/22 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C11/22 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

Abstract: Techniques and mechanisms for operating a ferroelectric (FE) circuit element as a cell of a crossbar memory array. In an embodiment, the crossbar memory array comprises a bit line, a word line, and a data storage cell which includes a circuit element that extends to each of the bit line and the word line. The data storage cell is a FE circuit element which comprises terminals, each at a different respective one of the bit line or the word line, and one or more material layers between said terminals. One such layer comprises a FE nitride or a FE oxide. The FE circuit element is operable to selectively enable, or disable, operation as a diode. In another embodiment, the memory array is coupled to circuitry which corresponds a given mode of operation of the FE circuit element to a particular data bit value.

公开(公告)号：US20240105718A1

公开(公告)日：2024-03-28

申请号：US17934251

申请日：2022-09-22

Applicant: Intel Corporation

Inventor： Tao Chu ,  Guowei Xu ,  Minwoo Jang ,  Yanbin Luo ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/778 ,  H01L29/78696

Abstract: Methods for fabricating an integrated circuit (IC) device with a protection liner between doped semiconductor regions are provided. An example IC device includes a channel material having a first face and a second face opposite the first face, a first doped region and a second doped region in the channel material, extending from the second face towards the first face by a first distance; and an insulator structure in a portion of the channel material between the first and second doped regions, the insulator structure extending from the second face towards the first face by a second distance greater than the first distance. The insulator structure includes a first portion between the second face and the first distance and a second portion between first distance and the second distance. The insulator structure includes a liner material on sidewalls of the first portion but absent on sidewalls of the second portion.

公开(公告)号：US20230413684A1

公开(公告)日：2023-12-21

申请号：US17843976

申请日：2022-06-18

Applicant: Intel Corporation

Inventor： Punyashloka Debashis ,  Hai Li ,  Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young

IPC: H01L43/10 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06 ,  H01L43/14

CPC classification number: H01L43/10 ,  H01L27/228 ,  H01L43/04 ,  H01L43/065 ,  H01L43/14

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

公开(公告)号：US20230317729A1

公开(公告)日：2023-10-05

申请号：US17710584

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Dmitri Evgenievich Nikonov ,  Chia-Ching Lin ,  Hai Li ,  Ian Alexander Young ,  Julien Sebot ,  Punyashloka Debashis

IPC: H01L27/118 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/11803 ,  H01L29/78391 ,  H01L29/66984

Abstract: In one embodiment, an integrated circuit apparatus includes a plurality of metallization layers, each metallization layer comprising voltage supply lines and signal lines. The apparatus also includes logic circuits formed between respective pairs of metallization layers, with each logic circuit comprising non-CMOS logic devices to perform an operation on a respective bit of an input set of bits. The non-CMOS logic devices may include one or more of ferroelectric field-effect transistor (FeFET) devices or spintronic logic devices (e.g., magnetoelectric spin orbit (MESO) devices or ferroelectric spin orbit logic (FSOL) devices), and each logic circuit may be formed on a different vertical plane within the apparatus.

公开(公告)号：US11621391B2

公开(公告)日：2023-04-04

申请号：US16236060

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sasikanth Manipatruni ,  Tanay Gosavi ,  Dmitri Nikonov ,  Kaan Oguz ,  Ian A. Young

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  G11C11/14 ,  H01L27/11

Abstract: A memory device comprises an interconnect comprises a spin orbit coupling (SOC) material. A free magnetic layer is on the interconnect, a barrier material is over the free magnetic layer and a fixed magnetic layer is over the barrier material, wherein the free magnetic layer comprises an antiferromagnet. In another embodiment, memory device comprises a spin orbit coupling (SOC) interconnect and an antiferromagnet (AFM) free magnetic layer is on the interconnect. A ferromagnetic magnetic tunnel junction (MTJ) device is on the AFM free magnetic layer, wherein the ferromagnetic MTJ comprises a free magnet layer, a fixed magnet layer, and a barrier material between the free magnet layer and the fixed magnet layer.

公开(公告)号：US20230086080A1

公开(公告)日：2023-03-23

申请号：US17482131

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Dmitri Evgenievich Nikonov ,  Ian Alexander Young ,  John J. Plombon ,  Hai Li ,  Kaan Oguz ,  Tanay A. Gosavi ,  Emily Walker

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: In one embodiment, an apparatus includes a magnet, a first structure, and a second structure. The first structure includes a first conductive trace and a magnetoelectric material. The first conductive trace is coupled to an input voltage terminal, and the magnetoelectric material is coupled to the first conductive trace and the magnet. The second structure includes a superlattice structure and a second conductive trace. The superlattice structure includes one or more topological insulator materials. Moreover, the superlattice structure is coupled to the magnet and the second conductive trace, and the second conductive trace is coupled to an output voltage terminal.