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公开(公告)号：US20170243956A1
公开(公告)日：2017-08-24
申请号：US15482040
申请日：2017-04-07
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/66 , H01L21/3065 , H01L21/308 , H01L21/02 , H01L21/306
CPC分类号： H01L21/3086 , H01L21/02164 , H01L21/02233 , H01L21/02238 , H01L21/02255 , H01L21/30604 , H01L21/3065 , H01L21/3081 , H01L21/31 , H01L21/324 , H01L29/66795
摘要： A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etch to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin ends; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etch to remove a portion of the second cut fin.
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公开(公告)号：US20170194499A1
公开(公告)日：2017-07-06
申请号：US15462644
申请日：2017-03-17
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
IPC分类号： H01L29/78 , H01L29/423 , H01L21/02 , H01L29/66 , H01L21/321
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure including a semiconductor material portion located on a substrate and extending along a lengthwise direction, a gate stack overlying a portion of the semiconductor material portion, and a first low-k spacer portion and a second low-k spacer portion abutting the gate stack and spaced from each other by the gate stack along said lengthwise direction. The first low-k spacer portion and the second low-k spacer portion each part of a recessed dummy gate structure on the substrate and a sacrificial spacer with gaps around and above a portion of the dummy gate stack. The gaps are filled in with the first low-k spacer portion and the second low-k spacer portion.
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公开(公告)号：US09673083B2
公开(公告)日：2017-06-06
申请号：US14608729
申请日：2015-01-29
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L21/265 , H01L21/3115 , H01L21/02 , H01L21/308
CPC分类号： H01L21/76213 , H01L21/02238 , H01L21/02255 , H01L21/26506 , H01L21/3083 , H01L21/31155 , H01L21/76224 , H01L29/66795
摘要： One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.
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公开(公告)号：US20170148894A1
公开(公告)日：2017-05-25
申请号：US14952549
申请日：2015-11-25
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure formed based on forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
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公开(公告)号：US09660050B1
公开(公告)日：2017-05-23
申请号：US14952549
申请日：2015-11-25
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/7856 , H01L21/0217 , H01L21/28141 , H01L21/3212 , H01L29/42364 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66575 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure formed based on forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.
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公开(公告)号：US20170084690A1
公开(公告)日：2017-03-23
申请号：US15202983
申请日：2016-07-06
发明人： Kangguo Cheng , Xin Miao , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/06 , H01L29/66 , H01L29/423 , H01L21/02
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/02236 , H01L21/02238 , H01L21/02252 , H01L21/02532 , H01L21/02603 , H01L21/26566 , H01L21/823807 , H01L21/84 , H01L27/092 , H01L27/0922 , H01L27/1203 , H01L29/0649 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66742 , H01L29/66795 , H01L29/775 , H01L29/78606 , H01L29/78618 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： A method of making a nanowire device incudes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.
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公开(公告)号：US20170054004A1
公开(公告)日：2017-02-23
申请号：US15244067
申请日：2016-08-23
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/66 , H01L21/768 , H01L21/28 , H01L21/02
CPC分类号： H01L29/66553 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28079 , H01L21/76897 , H01L29/41791 , H01L29/6653 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.
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公开(公告)号：US20170047226A1
公开(公告)日：2017-02-16
申请号：US15227142
申请日：2016-08-03
发明人： Kangguo Cheng , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L21/285 , H01L29/45 , H01L29/08 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28518 , H01L21/283 , H01L21/76897 , H01L21/823418 , H01L21/823431 , H01L21/823475 , H01L27/0886 , H01L29/0847 , H01L29/41791 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66795 , H01L29/7851 , H01L2029/7858
摘要： A method of making a semiconductor device includes forming a recessed fin in a substrate, the recessed fin being substantially flush with a surface of the substrate; performing an epitaxial growth process over the recessed fin to form a source/drain over the recessed fin; and disposing a conductive metal around the source/drain.
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公开(公告)号：US09570583B2
公开(公告)日：2017-02-14
申请号：US15255628
申请日：2016-09-02
发明人： Xiuyu Cai , Kangguo Cheng , Ali Khakifirooz , Ruilong Xie
CPC分类号： H01L29/66545 , H01L21/0337 , H01L21/283 , H01L21/3083 , H01L21/76825 , H01L21/76829 , H01L21/76834 , H01L21/76897 , H01L29/0649 , H01L29/4966 , H01L29/6653 , H01L29/66553 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： Embodiments of the present invention may include methods of incorporating an embedded etch barrier layer into the replacement metal gate layer of field effect transistors (FETs) having replacement metal gates, as well as the structure formed thereby. The embedded etch stop layer may be composed of embedded dopant atoms and may be formed using ion implantation. The embedded etch stop layer may make the removal of replacement metal gate layers easier and more controllable, providing horizontal surfaces and determined depths to serve as the base for gate cap formation. The gate cap may insulate the gate from adjacent self-aligned electrical contacts.
摘要翻译： 本发明的实施例可以包括将嵌入的蚀刻阻挡层结合到具有替换金属栅极的场效应晶体管（FET）的替换金属栅极层以及由此形成的结构的方法。 嵌入的蚀刻停止层可以由嵌入的掺杂剂原子组成，并且可以使用离子注入形成。 嵌入的蚀刻停止层可以使得替换金属栅极层的移除更容易和更可控，从而提供水平表面和确定的深度以用作栅极盖形成的基底。 栅极帽可以将栅极与相邻的自对准电触头绝缘。
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公开(公告)号：US09520392B1
公开(公告)日：2016-12-13
申请号：US14954050
申请日：2015-11-30
发明人： Kangguo Cheng , Junli Wang , Ruilong Xie , Tenko Yamashita
IPC分类号： H01L29/94 , H01L27/07 , H01L29/06 , H01L21/308 , H01L21/225
CPC分类号： H01L27/0629 , H01L21/3083 , H01L21/3086 , H01L21/823431 , H01L27/0733 , H01L29/1083 , H01L29/66174 , H01L29/66537 , H01L29/6656 , H01L29/785 , H01L29/93
摘要： A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.
摘要翻译： 半导体器件包括在第一区域上具有鳍式场效应晶体管（finFET）的半导体衬底和在第二区域上的鳍变容二极管。 finFET包括从其上finFET表面延伸到第一区域的上表面以限定第一总鳍高度的第一半导体鳍片。 翅片变容二极管包括从其上变性反应器表面延伸到第二区域的上表面的第二半导体鳍片，以限定与鳍片鳍片的第一总鳍片高度不同的第二总翅片高度。
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