公开(公告)号：US06963620B2

公开(公告)日：2005-11-08

申请号：US10284342

申请日：2002-10-31

申请人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Kang-Yoon Lee ,  Eunseok Song ,  Jeong Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03C3/09 ,  H04L27/04 ,  H03D3/24 ,  H04L27/12 ,  H04L27/20

CPC分类号： H03C3/0966 ,  H03C3/0933

摘要： A translational-loop transmitter generates RF signals using at most one phase-locked-loop (PLL) circuit. In one embodiment, a single PLL generates two local oscillation signals. The first oscillation signal is mixed with a baseband signal to generate an intermediate frequency signal. The second oscillation signal is input into the translational loop to adjust a voltage-controlled oscillator to the desired carrier frequency. In order to perform this type of modulation, the frequencies of the local oscillation signals are set so that they are harmonically related to one another relative to the carrier frequency. Other embodiments generate only one oscillation signal. Under these conditions, the intermediate frequency signal is generated using the oscillation signal, and a frequency divider in the translational loop is used to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. In still other embodiments, a transmitter signal is generated without using any phase-locked-loop circuits. This is accomplished by generating an intermediate frequency signal using a crystal oscillator, and then using a frequency divider in a feedback loop to generate a control signal for adjusting the voltage-controlled oscillator to the carrier frequency. By minimizing the number of phase-locked-loop circuits in the transmitter, the size, cost, and power requirements of mobile handsets may be significantly reduced.

摘要翻译： 平移环路发射器使用至多一个锁相环（PLL）电路产生RF信号。 在一个实施例中，单个PLL产生两个本地振荡信号。 第一振荡信号与基带信号混合以产生中频信号。 第二振荡信号被输入到平移回路中，以将压控振荡器调整到期望的载波频率。 为了执行这种类型的调制，本地振荡信号的频率被设置为使得它们相对于载波频率彼此谐波相关。 其他实施例仅产生一个振荡信号。 在这些条件下，使用振荡信号产生中频信号，并且使用平移环路中的分频器产生用于将压控振荡器调节到载波频率的控制信号。 在其他实施例中，产生发射机信号而不使用任何锁相环电路。 这是通过使用晶体振荡器产生中频信号，然后在反馈环路中使用分频器来产生用于将压控振荡器调节到载波频率的控制信号来实现的。 通过最小化发射机中的锁相环电路的数量，移动手机的尺寸，成本和功率要求可能会大大降低。

公开(公告)号：US06952125B2

公开(公告)日：2005-10-04

申请号：US10689986

申请日：2003-10-22

申请人： Youngho Ahn ,  Eunseok Song ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Youngho Ahn ,  Eunseok Song ,  Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H03L7/197 ,  H03L7/06 ,  H03L7/08

CPC分类号： H03L7/1978

摘要： A system and method for improving the signal-to-noise ratio of a frequency generator suppresses phase noise and noise generated from mismatches in the internal generator circuits. This is accomplished using a modulation scheme which shifts spurious noise signals outside the loop bandwidth of the generator. When shifted in this manner, the noise signals maybe removed entirely or to any desired degree using, for example, a filter located along the signal path of the generator. In one embodiment, a Sigma-Delta modulator controls the value of a pulse-swallow frequency divider situated along a feedback path of a phase-locked loop to achieve a desired level of noise suppression. In another embodiment, a reference signal input into a phase-locked loop is modulated to effect noise suppression. In another embodiment, the foregoing forms of modulation are combined to accomplish the desired frequency shift. Through these modulation techniques, the signal-to-noise ratio of the frequency generator may be substantially improved while simultaneously achieving faster lock times.

摘要翻译： 用于提高频率发生器的信噪比的系统和方法抑制由内部发生器电路中的失配产生的相位噪声和噪声。 这是使用将发生器的环路带宽之外的杂散噪声信号移位的调制方案来实现的。 当以这种方式移位时，噪声信号可以使用例如沿着发生器的信号路径定位的滤波器被完全去除或达到任何期望的程度。 在一个实施例中，Σ-Δ调制器控制沿着锁相环路的反馈路径设置的脉冲吞咽分频器的值，以实现期望的噪声抑制水平。 在另一个实施例中，输入到锁相环的参考信号被调制以实现噪声抑制。 在另一个实施例中，组合上述形式的调制以实现期望的频移。 通过这些调制技术，可以显着提高频率发生器的信噪比，同时实现更快的锁定时间。

公开(公告)号：US20050045986A1

公开(公告)日：2005-03-03

申请号：US10927012

申请日：2004-08-27

申请人： Yido Koo ,  Hyungki Huh ,  Kang Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

发明人： Yido Koo ,  Hyungki Huh ,  Kang Lee ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC分类号： H01L20060101 ,  H01L23/64 ,  H01L29/00

CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from first and second wires which connect a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a third and fourth wires which connect a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a third conductor between the pins. The third conductor may include one or more bonding wires and the I/O pins are preferably ones which are adjacent one another. However, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. In another embodiment, connection between the first and second I/O pins is established by making the I/O pins have a unitary construction. In another embodiment, connection between the first and second I/O pins is established by a metallization layer located either on the surface of the package substrate or within this substrate. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一和第二引线形成，以及连接芯片上的第二焊盘的第三和第四引线 到包的第二个I / O引脚。 为了完成电感线圈，第一和第二I / O引脚通过引脚之间的第三根导体连接。 第三导体可以包括一个或多个接合线，并且I / O引脚优选地彼此相邻。 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 在另一个实施例中，通过使I / O引脚具有整体结构来建立第一和第二I / O引脚之间的连接。 在另一个实施例中，第一和第二I / O引脚之间的连接由位于封装基板的表面上或者在该基板内的金属化层建立。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

公开(公告)号：US07952435B2

公开(公告)日：2011-05-31

申请号：US11976912

申请日：2007-10-29

申请人： Seung-Wook Lee ,  Joonbac Park ,  Jeong Woo Lee ,  Su Won Kang ,  Kyeongho Lee

发明人： Seung-Wook Lee ,  Joonbac Park ,  Jeong Woo Lee ,  Su Won Kang ,  Kyeongho Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L1/026 ,  H03L7/113 ,  H03L7/187

摘要： Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time.

摘要翻译： 锁相环的实施例和用于补偿其温度的方法可以输出用于输出根据温度变化补偿的期望锁相环的压控振荡器的初始调谐数字值。 锁相环的实施例和用于补偿其温度的方法可以同时进行数字粗调和模拟微调以在有限的时间内补偿温度。

公开(公告)号：US20080026696A1

公开(公告)日：2008-01-31

申请号：US11878939

申请日：2007-07-27

申请人： Hyo Choi ,  Jin Jeon ,  Dae Kim ,  Kyeongho Lee ,  Sang Shim ,  Won Song ,  Jeong Kim

发明人： Hyo Choi ,  Jin Jeon ,  Dae Kim ,  Kyeongho Lee ,  Sang Shim ,  Won Song ,  Jeong Kim

IPC分类号： H04B7/00

CPC分类号： H04M1/6066 ,  H04M2250/02 ,  H04M2250/06 ,  H04W4/18 ,  H04W52/0216 ,  H04W52/0219 ,  H04W74/06 ,  H04W84/12 ,  H04W84/18 ,  H04W88/06 ,  Y02D70/142 ,  Y02D70/144

摘要： Embodiments of methods and systems according to the application can transmit voice data by using a wireless LAN and a Bluetooth. One system embodiment can include a headset, an AP, and a terminal device to communicate with the headset according to a first protocol (e.g., Bluetooth) to transmit downlink voice data to the headset and to receive uplink voice data from the headset and to communicate with the AP according to a second protocol (e.g., wireless LAN) to transmit the uplink voice data to the AP and to receive the downlink voice data from the AP. The terminal device can receive the downlink voice data from the AP after the terminal device sends a PS-Poll frame to the AP within a period during which a transmission/reception between the terminal device and the headset is not to be performed.

摘要翻译： 根据应用的方法和系统的实施例可以通过使用无线LAN和蓝牙来发送语音数据。 一个系统实施例可以包括头戴式耳机，AP和终端设备，以根据第一协议（例如，蓝牙）与头戴式耳机进行通信，以将下行语音数据发送到头戴式耳机，并从耳机接收上行语音数据并进行通信 根据第二协议的AP（例如，无线LAN）将上行语音数据发送到AP并从AP接收下行语音数据。 在终端设备和耳机之间的发送/接收不被执行的时间段内，终端设备可以在终端设备向AP发送PS-Poll帧之后从AP接收下行链路语音数据。

公开(公告)号：US07071535B2

公开(公告)日：2006-07-04

申请号：US10927152

申请日：2004-08-27

申请人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonban Park ,  Kyeongho Lee

发明人： Yido Koo ,  Hyungki Huh ,  Kang Yoon Lee ,  Jeong-Woo Lee ,  Joonban Park ,  Kyeongho Lee

IPC分类号： H01L29/00 ,  H03B7/14

CPC分类号： H01L23/642 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An integrated circuit package includes an inductance loop formed from a connection of lead wires and one or more input/output (I/O) package pins. In one embodiment, the inductance loop is formed from a first wire which connects a first bonding pad on the integrated circuit chip to a first I/O pin of the package and a second wire which connects a second bonding pad on the chip to a second I/O pin of the package. To complete the inductor loop, the first and second I/O pins are connected by a conductive bridge between the pins. The bridge may be formed by making the I/O pins have a unitary construction. In another embodiment, the bridge is formed by a metallization layer located either on the surface of the package substrate or within this substrate. The I/O pins are preferably ones which are adjacent one another; however, the loop may be formed from non-adjacent connections of I/O pins based, for example, on loop-length requirements, space considerations, and/or other design or functional factors. By forming the inductor loop within the limits of the integrated circuit package, a substantial reduction in space requirements is realized, which, in turn, promotes miniaturization. Also, the integrated circuit may be implemented in any one of a variety of systems, at least one parameter of which is controlled by the length of the inductor loop of the package.

摘要翻译： 集成电路封装包括由引线和一个或多个输入/输出（I / O）封装引脚的连接形成的电感回路。 在一个实施例中，电感回路由将集成电路芯片上的第一接合焊盘连接到封装的第一I / O引脚的第一引线和将芯片上的第二接合焊盘连接到第二引线的第二引线形成 封装的I / O引脚。 为了完成电感环路，第一和第二I / O引脚通过引脚之间的导电桥连接。 可以通过使I / O引脚具有单一结构来形成桥。 在另一个实施例中，桥由位于封装衬底的表面上或在该衬底内的金属化层形成。 I / O引脚优选为彼此相邻的引脚; 然而，环路可以基于例如环路长度要求，空间考虑和/或其他设计或功能因素的I / O引脚的不相邻连接形成。 通过在集成电路封装的极限内形成电感器回路，实现了空间要求的显着降低，这反过来促进了小型化。 此外，集成电路可以在各种系统中的任何一个中实现，其中的至少一个参数由封装的电感器环的长度来控制。

公开(公告)号：US5905769A

公开(公告)日：1999-05-18

申请号：US646450

申请日：1996-05-07

申请人： Kyeongho Lee ,  Deog-Kyon Jeong

发明人： Kyeongho Lee ,  Deog-Kyon Jeong

IPC分类号： H04L7/00 ,  H04L7/033 ,  H04L7/04 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  H03D3/24

CPC分类号： H04N7/52 ,  H04L7/0337 ,  H04N21/4305 ,  H04N7/083 ,  H04L2007/045 ,  H04L7/0008

摘要： A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it signal into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler oversamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.

摘要翻译： 公开了一种接收多通道数字串行编码信号并将其转换成同步的二进制字符集的方法和装置。 电荷泵锁相环接收传输的参考时钟并从参考时钟导出多相时钟。 多相时钟用于控制多个多位块组合电路。 每个汇编电路接收数字信号的一个通道并产生多位块或字符。 多比特块组合电路包括过采样器，数字锁相环和字节同步器。 过采样器在多相时钟的控制下对接收到的数字信号进行过采样，并产生过采样二进制数据序列。 数字锁相环接收过采样数据，并根据样本的偏斜特性从中选择样本。 字节同步器将选定位的序列组合成位块或字符。 通道间同步器接收由多位块组合电路中的每一个产生的字符作为输入，并且选择性地延迟所接收字符的输出，以便使每个通道的字符彼此同步。

公开(公告)号：US20080025262A1

公开(公告)日：2008-01-31

申请号：US11878937

申请日：2007-07-27

申请人： Jeong Kim ,  Hyo Choi ,  Jin Jeon ,  Dae Kim ,  Kyeongho Lee ,  Sang Shim ,  Won Song

发明人： Jeong Kim ,  Hyo Choi ,  Jin Jeon ,  Dae Kim ,  Kyeongho Lee ,  Sang Shim ,  Won Song

IPC分类号： H04Q7/00

CPC分类号： H04W36/0083 ,  H04Q2213/13098 ,  H04Q2213/13298 ,  H04Q2213/13389 ,  H04W36/14 ,  H04W88/06

摘要： Embodiments of systems (e.g., the terminal apparatus) and methods according to the application can perform a handoff from a WiBro (wireless broadband) service to a wireless LAN service or from a WIMAX (worldwide interoperability for microwave access) service to a wireless LAN service. One embodiment can perform a communication according to a WIMAX or WiBro standard and, upon entering into an area where a communication conforming to a wireless LAN standard is available, perform a communication according to the wireless LAN standard.

摘要翻译： 根据应用的系统（例如，终端设备）和方法的实施例可以执行从WiBro（无线宽带）服务到无线LAN服务或从WIMAX（全球微波接入互操作性）服务到无线LAN服务的切换 。 一个实施例可以根据WIMAX或WiBro标准执行通信，并且在进入符合无线LAN标准的通信可用的区域时，根据无线LAN标准执行通信。

公开(公告)号：US6026124A

公开(公告)日：2000-02-15

申请号：US97021

申请日：1998-06-12

申请人： Kyeongho Lee ,  Deog-Kyon Jeong

发明人： Kyeongho Lee ,  Deog-Kyon Jeong

IPC分类号： H03M7/14 ,  H03M5/14 ,  H04L7/00 ,  H04L7/04 ,  H04L25/03 ,  H04L25/08 ,  H04L25/49 ,  H04N7/083 ,  H04N7/52 ,  H04N21/2368 ,  H04N21/434 ,  H04L25/34 ,  H03M13/00 ,  H04J3/24

CPC分类号： H04L25/085 ,  H04L25/03866 ,  H04L25/4915 ,  H04N21/2368 ,  H04N21/4341 ,  H04N7/083 ,  H04N7/52 ,  H04L2007/045 ,  H04L7/0008

摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical `1` signals in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including fewer than a minimum number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical `1` signals are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.In one embodiment, an input sequence of 9-bit data blocks is balanced to produce a DC-balanced sequence of characters. A shift register generator generates a pseudo-random binary sequence. Two bits of the pseudo-random binary sequence are logically combined to determine whether to invert another bit in the pseudo-random binary sequence, thereby cycling the pseudo-random binary sequence. A bit of the pseudo-random binary sequence is used as a criterion to selectively invert all the bits in the incoming 9-bit data block, thereby producing a 9-bit data block in an output stream that, over time, tends to be DC-balanced.

公开(公告)号：US5999571A

公开(公告)日：1999-12-07

申请号：US539816

申请日：1995-10-05

申请人： Yeshik Shin ,  Kyeongho Lee ,  Sungjoon Kim ,  David Lee

发明人： Yeshik Shin ,  Kyeongho Lee ,  Sungjoon Kim ,  David Lee

IPC分类号： H03M7/14 ,  H04L7/00 ,  H04L7/04 ,  H04L25/03 ,  H04L25/08 ,  H04L25/49 ,  H04N7/083 ,  H04N7/52 ,  H04J3/06 ,  H04J3/17 ,  H04L7/06

CPC分类号： H04N7/52 ,  H04L25/03866 ,  H04L25/085 ,  H04L25/4915 ,  H04N21/4305 ,  H04N7/083 ,  H04L2007/045 ,  H04L7/0008 ,  H04N21/23602 ,  H04N21/4342

摘要： A method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes is disclosed herein. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

摘要翻译： 本文公开了一种用于从数据字节的输入序列产生转换控制的直流平衡字符序列的方法和装置。 每个数据字节中的位根据每个数据字节中的逻辑转换的数量来选择性地补充，以便产生选择性补充的数据块。 然后在包括在先前编码为字符的选择性补充的数据块中的不同类型的逻辑值之前确定累积差异。 此外，还确定与被编码的选择性补充的数据块中的当前一个相关联的候选字符中的当前差异。 如果当前视差与累积视差的第一极性相反的极性，则候选字符被分配给选择性补充的数据块中的当前一个。 或者，如果当前视差是第一极性，则候选字符的补码被分配给选择性补充的数据块中的当前一个。 在高转换操作模式中，选择性地补充包括小于最小数量的逻辑转换的数据块内的位，使得每个这样的选择性补充的数据块包括超过最小数量的逻辑转换。 在低转换操作模式中，选择性地补充具有多于预定数量的逻辑转换的数据块内的位，使得每个这样的选择性补充的数据块包括小于逻辑转换的最大数量。