公开(公告)号：US20080203572A1

公开(公告)日：2008-08-28

申请号：US12111352

申请日：2008-04-29

申请人： Tetsuya KUROKAWA ,  Koji Arita

发明人： Tetsuya KUROKAWA ,  Koji Arita

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76879 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a semiconductor device having interconnects, reduced in leakage current between the interconnects and improved in the TDDB characteristic, which comprises an insulating interlayer 108, and interconnects 160 filled in grooves formed in the insulating interlayer, comprising a copper layer 124 mainly composed of copper, having the thickness smaller than the depth of the grooves, and a low-expansion metal layer 140, which is a metal layer having a heat expansion coefficient smaller than that of the copper layer, formed on the copper layer.

摘要翻译： 本发明提供一种具有互连的半导体器件，其互连之间的漏电流减小，TDDB特性得到改善，TDDB特性包括绝缘中间层108和填充在形成于绝缘中间层中的沟槽中的互连160，其包括主要组成的铜层124 的厚度小于沟槽深度的铜，以及形成在铜层上的具有小于铜层的热膨胀系数的金属层的低膨胀金属层140。

公开(公告)号：US07341937B2

公开(公告)日：2008-03-11

申请号：US11174595

申请日：2005-07-06

申请人： Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

发明人： Koji Arita ,  Masayoshi Tagami ,  Hidenobu Miyamoto

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/76808 ,  H01L21/76813

摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

摘要翻译： 公开了具有精密加工的双镶嵌结构的半导体器件。 半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有 沟槽图案。 至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。 光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。 使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。

公开(公告)号：US07074698B2

公开(公告)日：2006-07-11

申请号：US10766921

申请日：2004-01-30

申请人： Noboru Morita ,  Tatsuya Usami ,  Koichi Ohto ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

发明人： Noboru Morita ,  Tatsuya Usami ,  Koichi Ohto ,  Sadayuki Ohnishi ,  Koji Arita ,  Ryohei Kitao ,  Yoichi Sasaki

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： H01L21/02126 ,  C23C16/325 ,  C23C16/36 ,  C23C16/401 ,  C23C16/46 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3148 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76832 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a semiconductor device using a PECVD method is provided, which improves the adhesion strength of a deposited dielectric layer to an underlying layer and the reliability of the deposited dielectric layer. After placing a substrate in a chamber, a gas having a thermal conductivity of 0.1 W/mK or greater (e.g., H2 or He) is introduced into the chamber, thereby contacting the gas with the substrate for stabilization of a temperature of the substrate. A desired dielectric layer is deposited on or over the substrate in the chamber using a PECVD method after the step of introducing the gas. As the desired dielectric layer, a dielectric layer having a low dielectric constant, such as a SiCH, SiCHN, or SiOCH layer, is preferably used.

摘要翻译： 提供了使用PECVD方法制造半导体器件的方法，其提高了沉积的介电层对下层的粘附强度和沉积的介电层的可靠性。 在将基板放置在室中之后，将导热率为0.1W / mK以上的气体（例如H 2 H 2或He）引入到室内，从而使气体与基板接触 稳定基板的温度。 在引入气体的步骤之后，使用PECVD方法将期望的电介质层沉积在室中的衬底上或衬底上。 作为所需的介电层，优选使用具有低介电常数的介电层，例如SiCH，SiCHN或SiOCH层。

公开(公告)号：US20060141778A1

公开(公告)日：2006-06-29

申请号：US11359393

申请日：2006-02-23

申请人： Takashi Tonegawa ,  Koji Arita ,  Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Yoichi Sasaki ,  Sadayuki Ohnishi ,  Ryohei Kitao

发明人： Takashi Tonegawa ,  Koji Arita ,  Tatsuya Usami ,  Noboru Morita ,  Koichi Ohto ,  Yoichi Sasaki ,  Sadayuki Ohnishi ,  Ryohei Kitao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.

摘要翻译： 一种半导体器件的制造方法，包括在包括诸如MSQ，SiC和SiCN的有机低电介质膜的绝缘层中形成通孔的步骤，然后通过阻挡金属将布线材料包埋在通孔中。 根据该方法，使用能够代替由有机成分构成的基团（甲基）的He / H 2气体，在形成通路孔之后和隔离金属沉积之前进行等离子体处理 并用氢气覆盖暴露的有机低介电膜（MSQ）的表面，或者能够分解基团（甲基）而不去除有机低介电分子的He气体。 结果，低电介质膜（MSQ）的表面被重新形成为亲水性，因此提高了与阻挡金属的粘附性，从而可以防止隔离金属的分离和划痕的发生。

公开(公告)号：US06876030B2

公开(公告)日：2005-04-05

申请号：US09956556

申请日：2001-09-20

申请人： Kiyoshi Uchiyama ,  Yasuhiro Shimada ,  Koji Arita ,  Tatsuo Otsuki

发明人： Kiyoshi Uchiyama ,  Yasuhiro Shimada ,  Koji Arita ,  Tatsuo Otsuki

IPC分类号： B65G1/137 ,  G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/516 ,  H01L29/78391 ,  H01L29/7881

摘要： A semiconductor memory device includes a field-effect transistor with a gate electrode that has been formed over a semiconductor substrate with a ferroelectric layer interposed between the electrode and the substrate. The device includes a first insulating layer, which is insulated against a leakage current more fully than the ferroelectric layer, between the ferroelectric layer and the gate electrode.

摘要翻译： 半导体存储器件包括具有栅极电极的场效应晶体管，该栅极电极已经形成在半导体衬底上，其中介于电极和衬底之间的铁电层。 该器件包括第一绝缘层，其在铁电层和栅电极之间绝对抵抗比铁电层更全面的泄漏电流。

公开(公告)号：US20050048769A1

公开(公告)日：2005-03-03

申请号：US10892352

申请日：2004-07-16

申请人： Ryohei Kitao ,  Koji Arita

发明人： Ryohei Kitao ,  Koji Arita

IPC分类号： C25D7/12 ,  C25D21/12 ,  H01L21/288 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/2885 ,  H01L21/76877

摘要： A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.

摘要翻译： 提供一种制造半导体器件的方法，其提高了通过互连沟槽或通孔中的电解电镀工艺形成的导电层的填充性能，并且实现了自底向上性能的更高的面内均匀性 。 在半导体衬底上的电介质层中形成的互连沟槽和通路孔中的至少一个填充导电层的电解电镀工艺包括：以预定的积分电流密度执行电镀操作的第一步骤，该电镀操作是产品 电流密度，表示包含构成导电层的材料的电镀溶液的每单位面积的电流值和电镀时间，以及在比第一步骤低的电流密度下进行电镀操作的第二步骤。

公开(公告)号：US06469334B2

公开(公告)日：2002-10-22

申请号：US09821596

申请日：2001-03-29

申请人： Koji Arita ,  Shinichiro Hayashi ,  Tatsuo Otsuki ,  Carlos A. Paz de Araujo

发明人： Koji Arita ,  Shinichiro Hayashi ,  Tatsuo Otsuki ,  Carlos A. Paz de Araujo

IPC分类号： H01L2994

CPC分类号： H01L28/56 ,  H01L21/28291 ,  H01L29/516 ,  H01L29/78391

摘要： A ferroelectric FET having an interface insulator layer containing ZrO2. The ferroelectric FET includes a gate oxide layer, the interface insulator layer is located on the gate oxide layer, and ferroelectric layered superlattice material is located on the interface insulator layer, The interface insulator layer has a thickness of from 15 to 25 nanometers.

摘要翻译： 具有含有ZrO 2的界面绝缘体层的铁电FET。 铁电FET包括栅极氧化物层，界面绝缘体层位于栅极氧化物层上，并且铁电层状超晶格材料位于界面绝缘体层上。界面绝缘体层的厚度为15至25纳米。

公开(公告)号：US06404003B1

公开(公告)日：2002-06-11

申请号：US09362480

申请日：1999-07-28

申请人： Larry D. McMillan ,  Carlos A. Paz de Araujo ,  Koji Arita ,  Masamichi Azuma

发明人： Larry D. McMillan ,  Carlos A. Paz de Araujo ,  Koji Arita ,  Masamichi Azuma

IPC分类号： H01L27108

CPC分类号： C23C18/1216 ,  C23C18/1245 ,  C23C18/1279 ,  C23C18/1283 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： An integrated circuit capacitor containing a thin film delectric metal oxide is formed above a silicon germanium substrate. A silicon nitride diffusion barrier layer is deposited on a silicon germanium substrate to prevent evaporation of the substrate in subsequent heating steps. A silicon dioxide stress reduction layer is deposited on the diffusion barrier layer. A bottom electrode is formed on the stress reduction layer, then a liquid precursor is spun on the bottom electrode, dried at about 400° C., and annealed at between 600° C. and 850° C. to form a BST capacitor dielectric. A top electrode is deposited on the dielectric and annealed. The integrated circuit may also include a BiCMOS device, a HBT device or a MOSFET.

摘要翻译： 在硅锗基板上形成包含薄膜电介质金属氧化物的集成电路电容器。 在硅锗衬底上沉积氮化硅扩散阻挡层，以防止随后的加热步骤中衬底的蒸发。 二氧化硅应力降低层沉积在扩散阻挡层上。 在应力降低层上形成底部电极，然后在底部电极上旋转液体前体，在约400℃下干燥，并在600℃和850℃之间退火以形成BST电容器电介质。 顶部电极沉积在电介质上并退火。 集成电路还可以包括BiCMOS器件，HBT器件或MOSFET。

公开(公告)号：US06396095B1

公开(公告)日：2002-05-28

申请号：US09869522

申请日：2001-06-29

申请人： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

发明人： Yasuhiro Shimada ,  Koji Arita ,  Kiyoshi Uchiyama

IPC分类号： H01L2976

CPC分类号： G11C11/22 ,  H01L21/28291 ,  H01L29/42324 ,  H01L29/516 ,  H01L29/78391

摘要： Source/drain regions for a field effect transistor are defined in a semiconductor substrate with a channel region interposed therebetween. A first gate electrode is formed over the semiconductor substrate with an insulating film sandwiched therebetween and has a gate length shorter than the length of the channel region. A ferroelectric film is formed to cover the first gate electrode and to have both side portions thereof make contact with the insulating film. A second gate electrode is formed to cover the ferroelectric film.

摘要翻译： 用于场效应晶体管的源极/漏极区限定在其间插入沟道区的半导体衬底中。 第一栅电极形成在半导体衬底之上，绝缘膜夹在其间，栅极长度短于沟道区的长度。 形成铁电膜以覆盖第一栅电极并且使其两侧部分与绝缘膜接触。 形成第二栅电极以覆盖铁电体膜。

公开(公告)号：US06255121B1

公开(公告)日：2001-07-03

申请号：US09258489

申请日：1999-02-26

申请人： Koji Arita ,  Shinichiro Hayashi ,  Tatsuo Otsuki ,  Carlos A. Paz de Araujo

发明人： Koji Arita ,  Shinichiro Hayashi ,  Tatsuo Otsuki ,  Carlos A. Paz de Araujo

IPC分类号： H01L2100

CPC分类号： H01L28/56 ,  H01L21/28291 ,  H01L29/516 ,  H01L29/78391

摘要： A method for forming an interface insulator layer in a ferroelectric FET memory, in which a liquid precursor is applied to a semiconductor substrate. Preferably, the liquid precursor is an enhanced metalorganic decomposition (“EMOD”) precursor, applied using a liquid-source misted deposition technique. Preferably, the EMOD precursor solution applied to the substrate contains metal ethylhexanoates containing metal moieties in relative molar proportions for forming an interface insulator layer containing ZrO2, CeO2, Y2O3 or (Ce1-xZrx)O2, wherein 0≦x≦1.

摘要翻译： 一种用于在铁电FET存储器中形成界面绝缘体层的方法，其中将液体前体施加到半导体衬底。 优选地，液体前体是使用液体源雾化沉积技术施加的增强的金属有机分解（“EMOD”）前体。 优选地，施加到基底上的EMOD前体溶液含有相对摩尔比例含有金属部分的金属乙基己酸，以形成含有ZrO 2，CeO 2，Y 2 O 3或（Ce 1-x Zr x）O 2的界面绝缘体层，其中0≤x≤1。